Architecture evaluation for power-efficient FPGAs

Fei Li, Deming Chen, Lei He, Jason Cong

Research output: Contribution to conferencePaper

Abstract

This paper presents a flexible FPGA architecture evaluation framework, named fpgaEVA-LP, for power efficiency analysis of LUT-based FPGA architectures. Our work has several contributions: (i) We develop a mixed-level FPGA power model that combines switch-level models for interconnects and macromodels for LUTs; (ii) We develop a tool that automatically generates a back-annotated gate-level netlist with post-layout extracted capacitances and delays; (iii) We develop a cycle-accurate power simulator based on our power model. It carries out gate-level simulation under real delay model and is able to capture glitch power; (iv) Using the frame work fpgaEVA-LP, we study the power efficiency of FPGAs, in 0.10um technology, under various settings of architecture parameters such as LUT sizes, cluster sizes and wire segmentation schemes and reach several important conclusions. We also present the detailed power consumption distribution among different FPGA components and shed light on the potential opportunities of power optimization for future FPGA designs (e.g., ≤ 0.10um technology).

Original languageEnglish (US)
Pages175-184
Number of pages10
StatePublished - Jul 17 2003
EventACM/SIGDA 11th ACM International Symposium on Field Programmable Gate Arrays - Monterey, CA, United States
Duration: Feb 23 2003Feb 25 2003

Other

OtherACM/SIGDA 11th ACM International Symposium on Field Programmable Gate Arrays
CountryUnited States
CityMonterey, CA
Period2/23/032/25/03

Keywords

  • FPGA architecture
  • FPGA power model
  • Low power design

ASJC Scopus subject areas

  • Computer Science(all)

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  • Cite this

    Li, F., Chen, D., He, L., & Cong, J. (2003). Architecture evaluation for power-efficient FPGAs. 175-184. Paper presented at ACM/SIGDA 11th ACM International Symposium on Field Programmable Gate Arrays, Monterey, CA, United States.