In this paper, we present the Sum of Powers-Of-Two (SPOT) algorithm transformation that results in a high-speed IIR filter architecture by forcing the first few coefficients of the denominator polynomial to powers of two or sums of powers of two. The SPOT transform achieves the same result as achieved by conventional pipelining techniques such as scattered look-ahead and minimum order augmentation but with significantly smaller pipelining overhead and similar sensitivity to coefficient quantization. For typical examples, the SPOT transform roughly saves 30% hardware complexity over existing techniques. Architectures for implementation of the transformed filter transfer functions have also been described.
|Original language||English (US)|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 2000|
|Event||Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000 - Geneva, Switz, Switzerland|
Duration: May 28 2000 → May 31 2000
ASJC Scopus subject areas
- Electrical and Electronic Engineering