Architecture-aware low-density parity-check codes

Mohammad M. Mansour, Naresh R Shanbhag

Research output: Contribution to journalArticlepeer-review


A high-throughput memory-efficient decoder architecture for architecture-aware low-density parity-check (LDPC) codes is proposed based on a novel turbo-decoding algorithm. The architecture benefits from various optimizations at the code-design, decoding algorithm, and decoder architecture levels. The interconnect complexity and memory overhead problems of current decoder implementations are reduced by designing structured or architecture-aware LDPC codes and employing a new turbo-decoding algorithm. An efficient memory architecture coupled with a scalable and dynamic transport network for storing and routing messages are proposed. Simulations demonstrate that the proposed architecture attains a throughput of 1.92 Gbits/s for a frame length of 2304 bits, and achieves savings of 89.13 % and 62.80 % in power consumption and silicon area over state-of-the-art, with a reduction of 60.5 % in interconnect wires.

Original languageEnglish (US)
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - 2003

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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