Architecture and performance evaluation of 3D CMOS-NEM FPGA

Keyphrases

• Nanoelectromechanical Systems 100%
• Performance Evaluation 100%
• 3-D CMOS 100%
• Architecture Evaluation 100%
• 3D Stacking 50%
• Nanoelectromechanical Relay 50%
• Delay Reduction 50%
• Performance Gain 25%
• Performance Enhancement 25%
• 3D Integration 25%
• Integration Techniques 25%
• Nanoelectromechanical Devices 25%
• Communication Channels 25%
• FPGA Routing 25%
• Local Communication 25%
• FPGA Placement 25%
• Connection Block 25%
• Configurable Logic Block 25%
• FPGA Look-up Table 25%
• 3D FPGA 25%
• Hybrid CMOS 25%
• Reconfigurable Architectures 25%
• Switch Block 25%
• Vertical Wire 25%

Computer Science

• Performance Evaluation 100%
• Performance Gain 100%
• Integration Technique 100%
• Architecture Evaluation 100%
• Enhance Performance 100%
• Configurable Logic Block 100%
• reconfigurable architecture 100%

Engineering

• Field Programmable Gate Arrays 100%
• Lookup Table 25%
• Communication Channel 25%
• Flow Routing 25%