Architecture and performance evaluation of 3D CMOS-NEM FPGA

Chen Dong, Chen Chen, Subhasish Mitra, Deming Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we introduce a reconfigurable architecture, named 3D CMOS-NEM FPGA, which utilizes Nanoelectromechanical (NEM) relays and 3D integration techniques synergistically. Unique features of our architecture include: hybrid CMOS-NEM FPGA look-up tables (LUTs) and configurable logic blocks (CLBs), NEM-based switch blocks (SBs) and connection blocks (CBs), and face-to-face 3D stacking. This architecture also has a built-in feature named direct link which is dedicated local communication channel using the short vertical wire between the two stacks to further enhance performance. A customized 3D FPGA placement and routing flow has been developed. By replacing CMOS components with NEM relays, a 19.5% delay reduction can be achieved compared to the baseline 2D CMOS architecture. 3D stacking together with NEM devices achieves a 31.5% delay reduction over the baseline. The best performance of this architecture is achieved by adding direct links, which provides a 41.9% performance gain over the baseline.

Original languageEnglish (US)
Title of host publication2011 13th International Workshop on System Level Interconnect Prediction, SLIP 2011
DOIs
StatePublished - Dec 1 2011
Event2011 13th International Workshop on System Level Interconnect Prediction, SLIP 2011 - San Diego, CA, United States
Duration: Jun 5 2011Jun 5 2011

Publication series

NameInternational Workshop on System Level Interconnect Prediction, SLIP

Other

Other2011 13th International Workshop on System Level Interconnect Prediction, SLIP 2011
CountryUnited States
CitySan Diego, CA
Period6/5/116/5/11

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Applied Mathematics

Cite this

Dong, C., Chen, C., Mitra, S., & Chen, D. (2011). Architecture and performance evaluation of 3D CMOS-NEM FPGA. In 2011 13th International Workshop on System Level Interconnect Prediction, SLIP 2011 [6135428] (International Workshop on System Level Interconnect Prediction, SLIP). https://doi.org/10.1109/SLIP.2011.6135428