Abstract
Speculative parallelization aggressively executes in parallel codes that cannot be fully parallelized by the compiler. Past proposals of hardware schemes have mostly focused on single-chip multiprocessors (CMPs), whose effectiveness is necessarily limited by their small size. Very few schemes have attempted this technique in the context of scalable shared-memory systems. In this paper, we present and evaluate a new hardware scheme for scalable speculative parallelization. This design needs relatively simple hardware and is efficiently integrated into a cache-coherent NUMA system. We have designed the scheme in a hierarchical manner that largely abstracts away the internals of the node. We effectively utilize a speculative CMP as the building block for our scheme. Simulations show that the architecture proposed delivers good speedups at a modest hardware cost. For a set of important non-analyzable scientific loops, we report average speedups of 4.2 for 16 processors. We show that support for per-word speculative state is required by our applications, or else the performance suffers greatly.
Original language | English (US) |
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Pages (from-to) | 13-24 |
Number of pages | 12 |
Journal | Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA |
DOIs | |
State | Published - 2000 |
Event | ISCA-27: The 27th Annual International Symposium on Computer Architecture - Vancouver, BC, Can Duration: Jun 10 2000 → Jun 14 2000 |
ASJC Scopus subject areas
- Hardware and Architecture