Architecting and Programming a Hardware-Incoherent Multiprocessor Cache Hierarchy

Wooil Kim, Sanket Tavarageri, P. Sadayappan, Josep Torrellas

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

New architectures for extreme-scale computing need to bedesigned for higher energy efficiency than current systems. One recently-proposed extreme-scale manycore radically simplifiesthe architecture, and proposes a cluster-based on-chip memory hierarchy withouthardware cache coherence. To program for such an environment, this paper proposes twoapproaches. They use shared-memory programmingeither inside clusters only, or both inside and across clusters. Both approaches rely on ISA support for writeback and self-invalidation operations. Our simulation results show thathardware-incoherent cache hierarchies with our support deliverreasonable performance for applications that were notwritten for such hierarchies. Specifically, forexecution within a cluster, the averageexecution time of the applications is 2% higher than with hardware cache coherence, for execution across multiple clusters, it is 5% higher than with hardware cache coherence. This is accomplished with minimal hardware support.

Original languageEnglish (US)
Title of host publicationProceedings - 2016 IEEE 30th International Parallel and Distributed Processing Symposium, IPDPS 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages555-565
Number of pages11
ISBN (Electronic)9781509021406
DOIs
StatePublished - Jul 18 2016
Event30th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2016 - Chicago, United States
Duration: May 23 2016May 27 2016

Publication series

NameProceedings - 2016 IEEE 30th International Parallel and Distributed Processing Symposium, IPDPS 2016

Other

Other30th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2016
CountryUnited States
CityChicago
Period5/23/165/27/16

Keywords

  • Cache coherence
  • Hardware-incoherent caches
  • Software-managed caches

ASJC Scopus subject areas

  • Computer Networks and Communications

Fingerprint Dive into the research topics of 'Architecting and Programming a Hardware-Incoherent Multiprocessor Cache Hierarchy'. Together they form a unique fingerprint.

Cite this