Abstract

This paper presents a hierarchical simulation methodology that enables accurate system evaluation under realistic faults and conditions. The methodology spans the entire range of analysis from the device level to the system level. In this study we focus on two low levels of the simulation hierarchy - the device level and the circuit level. The primary fault model is obtained via simulation of the transistor-level effect of radiation particles penetrating the device. The resulting current bursts constitute the first-level fault dictionary and are used in the circuit-level simulation to determine the impact on circuit latches and flip-flops. The resulting outputs are recorded in the fault dictionary and can be used to analyze the impact of transients at the higher simulation levels, i.e., the chip level and the system level. The study demonstrated that the proposed hierarchical fault injection methodology is able to precisely capture the generation of transients in digital devices and thus provides a basis for realistic system evaluation.

Original languageEnglish (US)
Pages260-265
Number of pages6
DOIs
StatePublished - Jan 1 1999
EventProceedings of the 1999 12th International Conference on VLSI Design - Goa, India
Duration: Jan 7 1999Jan 10 1999

Other

OtherProceedings of the 1999 12th International Conference on VLSI Design
CityGoa, India
Period1/7/991/10/99

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Kalbarczyk, Z., Patel, J., Lee, M. S., & Iyer, R. K. (1999). Approach to evaluating the effects of realistic faults in digital circuits. 260-265. Paper presented at Proceedings of the 1999 12th International Conference on VLSI Design, Goa, India, . https://doi.org/10.1109/icvd.1999.745158