Application of the latency insertion method to electro-thermal circuit analysis

D. Klokotov, J. Schutt-Ainé, W. Beyene, D. Mullen, M. Li, R. Schmitt, L. Yang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, a fast circuit simulation technique based on the Latency Insertion Method (LIM) is proposed for the electro-thermal analysis of circuits and high-performance systems. The method is applied to the modeling of on-chip and off-chip 3D-interconnect networks. The proposed method is shown to be capable of modeling both electrical and thermal phenomena occurring in high speed, high performance VLSI circuits at the pre-layout design stages.

Original languageEnglish (US)
Title of host publication2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011
Pages263-266
Number of pages4
DOIs
StatePublished - 2011
Event2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011 - San Jose, CA, United States
Duration: Oct 23 2011Oct 26 2011

Publication series

Name2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011

Other

Other2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011
Country/TerritoryUnited States
CitySan Jose, CA
Period10/23/1110/26/11

Keywords

  • IR drop
  • circuit simulation
  • electro-thermal analysis
  • latency insertion
  • power integrity

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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