Application of high pressure deuterium annealing for improving the hot carrier reliability of CMOS transistors

Lee Jinju, Kangguo Cheng, Zhi Chen, Karl Hess, Joseph W. Lyding, Kim Young-Kwang, Lee Seung, Kim Young-Wug, Suh Kwang-Pyuk

Research output: Contribution to journalArticle

Abstract

We present the effect of high pressure deuterium annealing on hot carrier reliability improvements of CMOS transistors. High pressure annealing increases the rate of deuterium incorporation at the SiO2/Si interface. We have achieved a significant lifetime improvement (90 ×) from fully processed wafers (four metal layers) with nitride sidewall spacers and SiON cap layers. The improvement was determined by comparing to wafers that were annealed in a conventional hydrogen forming gas anneal. The annealing time to achieve the same level of improvement is also significantly reduced. The increased incorporation of D at high pressure was confirmed by the secondary ion mass spectrometry characterization.

Original languageEnglish (US)
Pages (from-to)221-223
Number of pages3
JournalIEEE Electron Device Letters
Volume21
Issue number5
DOIs
StatePublished - May 1 2000

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Jinju, L., Cheng, K., Chen, Z., Hess, K., Lyding, J. W., Young-Kwang, K., Seung, L., Young-Wug, K., & Kwang-Pyuk, S. (2000). Application of high pressure deuterium annealing for improving the hot carrier reliability of CMOS transistors. IEEE Electron Device Letters, 21(5), 221-223. https://doi.org/10.1109/55.841302