We present the effect of high pressure deuterium annealing on hot carrier reliability improvements of CMOS transistors. High pressure annealing increases the rate of deuterium incorporation at the SiO2/Si interface. We have achieved a significant lifetime improvement (90 ×) from fully processed wafers (four metal layers) with nitride sidewall spacers and SiON cap layers. The improvement was determined by comparing to wafers that were annealed in a conventional hydrogen forming gas anneal. The annealing time to achieve the same level of improvement is also significantly reduced. The increased incorporation of D at high pressure was confirmed by the secondary ion mass spectrometry characterization.
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering