Abstract
Two compiler-assisted multiple-instruction word retry schemes for very long instruction word (VLIW) architectures are described. The first scheme compacts the compiler-generated hazard-free code with different degrees of rollback capability for scalar processors [14], and inserts no-ops in the scheduled code words. The second scheme employs a hardware read buffer [2] to resolve frequently occurring data hazards, and utilizes the compiler to resolve the remaining hazards.
Original language | English (US) |
---|---|
Pages | 51-58 |
Number of pages | 8 |
State | Published - 1995 |
Event | Proceedings of the 1995 Fault-Tolerant Parallel and Distributed Systems - Galveston, TX, USA Duration: Jun 13 1994 → Jun 14 1994 |
Other
Other | Proceedings of the 1995 Fault-Tolerant Parallel and Distributed Systems |
---|---|
City | Galveston, TX, USA |
Period | 6/13/94 → 6/14/94 |
ASJC Scopus subject areas
- General Computer Science