Application level hardware tracing for scaling post-silicon debug

Debjit Pal, Abhishek Sharma, Sandip Ray, Flavio M. De Paula, Shobha Vasudevan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We present a method for selecting trace messages for post-silicon validation of Systems-on-a-Chips (SoCs) with diverse usage scenarios. We model specifications of interacting flows in typical applications. Our method optimizes trace buffer utilization and flow specification coverage. We present debugging and root cause analysis of subtle bugs in the industry scale OpenSPARC T2 processor. We demonstrate that this scale is beyond the capacity of current tracing approaches. We achieve trace buffer utilization of 98.96% with a flow specification coverage of 94.3% (average). We localize bugs to 21.11% (average) of the potential root causes in our large-scale debugging effort.

Original languageEnglish (US)
Title of host publicationProceedings of the 55th Annual Design Automation Conference, DAC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
VolumePart F137710
ISBN (Print)9781450357005
DOIs
StatePublished - Jun 24 2018
Event55th Annual Design Automation Conference, DAC 2018 - San Francisco, United States
Duration: Jun 24 2018Jun 29 2018

Other

Other55th Annual Design Automation Conference, DAC 2018
CountryUnited States
CitySan Francisco
Period6/24/186/29/18

Fingerprint

Tracing
Silicon
Trace
Hardware
Debugging
Scaling
Specifications
Buffer
Coverage
Roots
Specification
Model Specification
Chip
Optimise
Industry
Scenarios
Demonstrate

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation

Cite this

Pal, D., Sharma, A., Ray, S., De Paula, F. M., & Vasudevan, S. (2018). Application level hardware tracing for scaling post-silicon debug. In Proceedings of the 55th Annual Design Automation Conference, DAC 2018 (Vol. Part F137710). [a92] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/3195970.3195992

Application level hardware tracing for scaling post-silicon debug. / Pal, Debjit; Sharma, Abhishek; Ray, Sandip; De Paula, Flavio M.; Vasudevan, Shobha.

Proceedings of the 55th Annual Design Automation Conference, DAC 2018. Vol. Part F137710 Institute of Electrical and Electronics Engineers Inc., 2018. a92.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Pal, D, Sharma, A, Ray, S, De Paula, FM & Vasudevan, S 2018, Application level hardware tracing for scaling post-silicon debug. in Proceedings of the 55th Annual Design Automation Conference, DAC 2018. vol. Part F137710, a92, Institute of Electrical and Electronics Engineers Inc., 55th Annual Design Automation Conference, DAC 2018, San Francisco, United States, 6/24/18. https://doi.org/10.1145/3195970.3195992
Pal D, Sharma A, Ray S, De Paula FM, Vasudevan S. Application level hardware tracing for scaling post-silicon debug. In Proceedings of the 55th Annual Design Automation Conference, DAC 2018. Vol. Part F137710. Institute of Electrical and Electronics Engineers Inc. 2018. a92 https://doi.org/10.1145/3195970.3195992
Pal, Debjit ; Sharma, Abhishek ; Ray, Sandip ; De Paula, Flavio M. ; Vasudevan, Shobha. / Application level hardware tracing for scaling post-silicon debug. Proceedings of the 55th Annual Design Automation Conference, DAC 2018. Vol. Part F137710 Institute of Electrical and Electronics Engineers Inc., 2018.
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