Multicore processors used in high-performance computing platforms place ever-increasing demands on efficient voltage regulator design. However, high clock frequency and power consumption of the processors have increased load current and its slew rate rapidly, posing stringent challenges for the voltage regulator design. Since a sudden load-current change incurs voltage overshoots or droops due to the limited bandwidth of voltage regulators, a tolerance window within the defined minimum and maximum voltage levels must be allowed for performance and reliability of the processors. A cost-effective regulation technique like adaptive voltage positioning uses the window by positioning the voltage level at light load-current near the upper limit to sustain negative spikes during the worst-case transient without crossing the lower limit. However, this often results in more processor power consumption than necessary since most of the load-current transients are usually smaller than the worst case. As a result, the voltage level stays much above the lower limit. In this paper, first, we analyze potential total power reduction of a high-performance quadcore processor when we can dynamically reposition regulator output voltage depending on individual core's power-states that affect processor load-current significantly. Our analysis using a 32nm predictive technology model shows that repositioning the regulator output voltage can reduce the power consumption of the processor by up to 29%. Second, we extend our analysis to consider each core's temperature and within-die spatial process variations that can affect leakage (thus total load) current substantially, which provides up to 5% additional power reduction.