Analytical expressions for power dissipation of macro-blocks in DSP architectures

S. Bobba, I. N. Hajj, Naresh R Shanbhag

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Power minimization is an important objective in present day VLSI design. Macromodels for power dissipation can be used to estimate power at a high-level of abstraction. High-level power estimation methods provide the designer with more flexibility to explore design trade-offs early in the design cycle. In this paper, we present closed-form analytical expressions for power consumption of macro-blocks in terms of the word-statistics. We present an analytical expression for total bit transition activity of a signal line in terms of the word-statistics. We also present analytical power models for macro-blocks in DSP architectures in terms of total bit transition activity and other parameters. Experimental results validating the analytical expressions are also included in this paper.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE International Conference on VLSI Design
PublisherIEEE Comp Soc
Pages358-363
Number of pages6
StatePublished - 1999
EventProceedings of the 1999 12th International Conference on VLSI Design - Goa, India
Duration: Jan 7 1999Jan 10 1999

Other

OtherProceedings of the 1999 12th International Conference on VLSI Design
CityGoa, India
Period1/7/991/10/99

ASJC Scopus subject areas

  • Engineering(all)

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