### Abstract

Accurate high-level power estimation methods are required for exploring the design space to obtain an optimal low-power circuit. DSP architectures are regular and they consist of inter-connected macro-blocks such as adders and multipliers. In [I], the power dissipation of macro-blocks was related to the average bit statistics. Given the input word-level statistics for a DSP architecture, the word-level statistics at all the internal signal lines can be computed analytically using transfer function evaluation or by propagating the statistics. In this paper, we present simple analytical expressions for computing the average bit statistics using the word-level statistics of the signal lines in a DSP architecture.

Original language | English (US) |
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Pages (from-to) | 33-36 |

Number of pages | 4 |

Journal | Proceedings - IEEE International Symposium on Circuits and Systems |

Volume | 6 |

State | Published - Jan 1 1998 |

Event | Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA Duration: May 31 1998 → Jun 3 1998 |

### ASJC Scopus subject areas

- Electrical and Electronic Engineering

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## Cite this

*Proceedings - IEEE International Symposium on Circuits and Systems*,

*6*, 33-36.