Analysis of System-Level ESD-Induced Soft Failures in a CMOS Microcontroller

This article presents a root-cause investigation of system-level electrostatic discharge-induced soft failures in a semi-custom microcontroller test chip. Sources of failures include clock glitches, reset glitches, and bit flips in memory. The affected circuit blocks are identified with the aid of a scan chain and memory read-out programs; on-chip voltage monitors allow us to establish whether those failures are correlated with the power supply noise. Simulations are used to study the spatial extent of the noise on the power nets and the signal pins. The effect of down-bonding on the supply noise is investigated using both measurement and simulation.