TY - JOUR
T1 - Analysis of PLL Clock Jitter in High-Speed Serial Links
AU - Hanumolu, Pavan Kumar
AU - Casper, Bryan
AU - Mooney, Randy
AU - Wei, Gu Yeon
AU - Moon, Un Ku
N1 - Funding Information:
Manuscript received May 1, 2003; revised July 2003. This work was supported by Intel Corporation, Hillsboro, OR. This paper was recommended by Guest Editor M. Perrott. K. P. Hanumolu and U. Moon are with the Department of Electrical and Computer Engineering, Oregon State University, Corvallis, OR 97331-3211 USA (e-mail: [email protected]). B. Casper and R. Mooney are with Intel Laboratories, Hillsboro, OR 97124 USA. G.-Y. Wei is with the Department of Electrical Engineering, Harvard University, Cambridge, MA 02138 USA. Digital Object Identifier 10.1109/TCSII.2003.819121 1The spectral content of the phase noise is still important for the receiver as timing recovery circuit can track low-frequency jitter. Because the scope of this paper is limited to the analysis of PLL jitter in serial links in general, we omit the discussion on this low-frequency jitter tracking of the timing recovery circuit. This kind of jitter tracking is generally considered a common knowledge by the design community.
PY - 2003/11
Y1 - 2003/11
N2 - We analyze the effects of transmitter and receiver phased-locked loop (PLL) phase noise, which translates to time-domain clock/data jitter, on the performance of high-speed transceivers. Analytical expressions are derived to incorporate both transmitter and receiver clock jitter into serial link operation. A method to calculate the worst-case noise margin degradation due to clock jitter is discussed in order to obviate impractical time-domain simulations. This analysis relies on the assumption that the channel is linear and time-invariant and, hence, can be characterized by an impulse response. A simple extension to equalized serial links is also presented. The analysis is verified through behavioral simulations using a realistic/measured channel model.
AB - We analyze the effects of transmitter and receiver phased-locked loop (PLL) phase noise, which translates to time-domain clock/data jitter, on the performance of high-speed transceivers. Analytical expressions are derived to incorporate both transmitter and receiver clock jitter into serial link operation. A method to calculate the worst-case noise margin degradation due to clock jitter is discussed in order to obviate impractical time-domain simulations. This analysis relies on the assumption that the channel is linear and time-invariant and, hence, can be characterized by an impulse response. A simple extension to equalized serial links is also presented. The analysis is verified through behavioral simulations using a realistic/measured channel model.
KW - Bit-error rate (BER)
KW - Eye diagrams
KW - Inter-symbol interference
KW - Jitter
KW - Phase noise
KW - Phase-locked loops (PLL)
KW - Serial links
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U2 - 10.1109/TCSII.2003.819121
DO - 10.1109/TCSII.2003.819121
M3 - Article
AN - SCOPUS:0345293098
SN - 1057-7130
VL - 50
SP - 879
EP - 886
JO - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
JF - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
IS - 11
ER -