Analysis of PLL Clock Jitter in High-Speed Serial Links

Pavan Kumar Hanumolu, Bryan Casper, Randy Mooney, Gu Yeon Wei, Un Ku Moon

Research output: Contribution to journalArticlepeer-review


We analyze the effects of transmitter and receiver phased-locked loop (PLL) phase noise, which translates to time-domain clock/data jitter, on the performance of high-speed transceivers. Analytical expressions are derived to incorporate both transmitter and receiver clock jitter into serial link operation. A method to calculate the worst-case noise margin degradation due to clock jitter is discussed in order to obviate impractical time-domain simulations. This analysis relies on the assumption that the channel is linear and time-invariant and, hence, can be characterized by an impulse response. A simple extension to equalized serial links is also presented. The analysis is verified through behavioral simulations using a realistic/measured channel model.

Original languageEnglish (US)
Pages (from-to)879-886
Number of pages8
JournalIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Issue number11
StatePublished - Nov 2003
Externally publishedYes


  • Bit-error rate (BER)
  • Eye diagrams
  • Inter-symbol interference
  • Jitter
  • Phase noise
  • Phase-locked loops (PLL)
  • Serial links

ASJC Scopus subject areas

  • Signal Processing
  • Electrical and Electronic Engineering


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