Abstract
A one-stage shuffle exchange network to be used as a processor-memory switch in a multiprocessor is described. The stochastic behavior of the network is studied under the assumption that any memory module is equally likely to be referenced. It is shown that under these assumptions the average number of passes through the network for an item of data to reach its destination can be made less than 2log//2N when N less than equivalent to 2**2**0 (N is the number of processors and memories). This can be achieved by using no more than four one-stage shuffle-exchange networks, each one consisting of N exchange elements.
| Original language | English (US) |
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| Pages | 116-123 |
| Number of pages | 8 |
| State | Published - 1980 |
| Externally published | Yes |
| Event | Proc of the Workshop on Interconnect Networks for Parallel and Distrib Process - Lafeyette, IN, USA Duration: Apr 21 1980 → Apr 22 1980 |
Conference
| Conference | Proc of the Workshop on Interconnect Networks for Parallel and Distrib Process |
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| City | Lafeyette, IN, USA |
| Period | 4/21/80 → 4/22/80 |
ASJC Scopus subject areas
- Engineering(all)