Analysis of digital circuit dynamic behavior with timed ternary decision diagrams for better-than-worst-case design

Modern logic optimization tools tend to optimize circuits in a balanced way so that all primary outputs (POs) have the similar delay close to the cycle time. However, in reality, certain POs will be exercised more frequently than the rest. Among the critical POs, some may be stabilized very quickly by input vectors, even if their topological delays from primary inputs are very long. Knowing the dynamic behavior of a circuit can help optimize the most commonly activated paths and help engineers understand how resilient a PO is against dynamic environmental variations such as voltage fluctuations. In this paper, we describe a tool to analyze the dynamic behavior of a digital circuit utilizing probabilistic information. The techniques exploit the use of timed ternary decision diagrams (tTDD) to encode stabilization conditions for POs. To compute probabilities based on a tTDD, we propose false assignment pruning and random variable compaction to preserve probability calculation accuracy. To deal with the scalability issue, this paper proposes a new circuit partitioning heuristic to reduce the inaccuracy introduced by partitioning. Compared to the timed simulation results, on average our tool has a mean absolute error of 1.7% and a root mean square error of 3.9% for MCNC benchmarks and a mean absolute error of 2.2% and a root mean square error of 4.8% for ISCAS benchmarks. Compared to a state-of-the-art dynamic behavior analysis tool, our tool is $15\times$ faster on average for MCNC benchmarks and $65\times$ faster on average for ISCAS benchmarks, and can also handle circuits that the previous tool cannot. This dynamic behavior analyzer would enable fast and effective circuit optimizations for better-than-worst-case design.