TY - JOUR
T1 - Analysis of charge-pump phase-locked loops
AU - Hanumolu, Pavan Kumar
AU - Brownlee, Merrick
AU - Mayaram, Kartikeya
AU - Moon, Un Ku
N1 - Funding Information:
Manuscript received November 14, 2003; revised February 26, 2004. This work was supported by Intel Corporation and by the Semiconductor Research Corporation. This paper was recommended by Associate Editor G.-Y. Wei.
PY - 2004/9
Y1 - 2004/9
N2 - In this paper, we present an exact analysis for third-order charge-pump phase-locked loops using state equations. Both the large-signal lock acquisition process and the small-signal linear tracking behavior are described using this analysis. The nonlinear state equations are linearized for the small-signal condition and the z-domain noise transfer functions are derived. A comparison to some of the existing analysis methods such as the impulse-invariant transformation and s-domain analysis is provided. The effect of the loop parameters and the reference frequency on the loop phase margin and stability is analyzed. The analysis is verified using behavioral simulations in MATLAB and SPECTRE.
AB - In this paper, we present an exact analysis for third-order charge-pump phase-locked loops using state equations. Both the large-signal lock acquisition process and the small-signal linear tracking behavior are described using this analysis. The nonlinear state equations are linearized for the small-signal condition and the z-domain noise transfer functions are derived. A comparison to some of the existing analysis methods such as the impulse-invariant transformation and s-domain analysis is provided. The effect of the loop parameters and the reference frequency on the loop phase margin and stability is analyzed. The analysis is verified using behavioral simulations in MATLAB and SPECTRE.
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U2 - 10.1109/TCSI.2004.834516
DO - 10.1109/TCSI.2004.834516
M3 - Article
AN - SCOPUS:4744340842
SN - 1057-7122
VL - 51
SP - 1665
EP - 1674
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 9
ER -