Analysis and optimization of I/O cache coherency strategies for SoC-FPGA device

Seung Won Min; Sitao Huang; Mohamed El-Hadedy; Jinjun Xiong; Deming Chen; Wen Mei Hwu

doi:10.1109/FPL.2019.00055

Analysis and optimization of I/O cache coherency strategies for SoC-FPGA device

Seung Won Min, Sitao Huang, Mohamed El-Hadedy, Jinjun Xiong, Deming Chen, Wen Mei Hwu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Unlike traditional PCIe-based FPGA accelerators, heterogeneous SoC-FPGA devices provide tighter integrations between software running on CPUs and hardware accelerators. Modern heterogeneous SoC-FPGA platforms support multiple I/O cache coherence options between CPUs and FPGAs, but these options can have inadvertent effects on the achieved bandwidths depending on applications and data access patterns. To provide the most efficient communications between CPUs and accelerators, understanding the data transaction behaviors and selecting the right I/O cache coherence method is essential. In this paper, we use Xilinx Zynq UltraScale+ as the SoC platform to show how certain I/O cache coherence method can perform better or worse in different situations, ultimately affecting the overall accelerator performances as well. Based on our analysis, we further explore possible software and hardware modifications to improve the I/O performances with different I/O cache coherence options. With our proposed modifications, the overall performance of SoC design can be averagely improved by 20%.

Original language	English (US)
Title of host publication	Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019
Editors	Ioannis Sourdis, Christos-Savvas Bouganis, Carlos Alvarez, Leonel Antonio Toledo Diaz, Pedro Valero, Xavier Martorell
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	301-306
Number of pages	6
ISBN (Electronic)	9781728148847
DOIs	https://doi.org/10.1109/FPL.2019.00055
State	Published - Sep 2019
Event	29th International Conferenceon Field-Programmable Logic and Applications, FPL 2019 - Barcelona, Spain Duration: Sep 9 2019 → Sep 13 2019

Publication series

Name	Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019

Conference

Conference	29th International Conferenceon Field-Programmable Logic and Applications, FPL 2019
Country/Territory	Spain
City	Barcelona
Period	9/9/19 → 9/13/19

Keywords

Cache
Cache coherence
FPGA
Heterogenous computing

ASJC Scopus subject areas

Instrumentation
Artificial Intelligence
Computer Science Applications
Hardware and Architecture

Online availability

10.1109/FPL.2019.00055

Library availability

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Min, S. W., Huang, S., El-Hadedy, M., Xiong, J., Chen, D., & Hwu, W. M. (2019). Analysis and optimization of I/O cache coherency strategies for SoC-FPGA device. In I. Sourdis, C.-S. Bouganis, C. Alvarez, L. A. Toledo Diaz, P. Valero, & X. Martorell (Eds.), Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019 (pp. 301-306). Article 8892094 (Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/FPL.2019.00055

Analysis and optimization of I/O cache coherency strategies for SoC-FPGA device. / Min, Seung Won; Huang, Sitao; El-Hadedy, Mohamed et al.
Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019. ed. / Ioannis Sourdis; Christos-Savvas Bouganis; Carlos Alvarez; Leonel Antonio Toledo Diaz; Pedro Valero; Xavier Martorell. Institute of Electrical and Electronics Engineers Inc., 2019. p. 301-306 8892094 (Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Min, SW, Huang, S, El-Hadedy, M, Xiong, J, Chen, D & Hwu, WM 2019, Analysis and optimization of I/O cache coherency strategies for SoC-FPGA device. in I Sourdis, C-S Bouganis, C Alvarez, LA Toledo Diaz, P Valero & X Martorell (eds), Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019., 8892094, Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019, Institute of Electrical and Electronics Engineers Inc., pp. 301-306, 29th International Conferenceon Field-Programmable Logic and Applications, FPL 2019, Barcelona, Spain, 9/9/19. https://doi.org/10.1109/FPL.2019.00055

Min SW, Huang S, El-Hadedy M, Xiong J, Chen D , Hwu WM. Analysis and optimization of I/O cache coherency strategies for SoC-FPGA device. In Sourdis I, Bouganis CS, Alvarez C, Toledo Diaz LA, Valero P, Martorell X, editors, Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 301-306. 8892094. (Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019). doi: 10.1109/FPL.2019.00055

Min, Seung Won ; Huang, Sitao ; El-Hadedy, Mohamed et al. / Analysis and optimization of I/O cache coherency strategies for SoC-FPGA device. Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019. editor / Ioannis Sourdis ; Christos-Savvas Bouganis ; Carlos Alvarez ; Leonel Antonio Toledo Diaz ; Pedro Valero ; Xavier Martorell. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 301-306 (Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019).

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AB - Unlike traditional PCIe-based FPGA accelerators, heterogeneous SoC-FPGA devices provide tighter integrations between software running on CPUs and hardware accelerators. Modern heterogeneous SoC-FPGA platforms support multiple I/O cache coherence options between CPUs and FPGAs, but these options can have inadvertent effects on the achieved bandwidths depending on applications and data access patterns. To provide the most efficient communications between CPUs and accelerators, understanding the data transaction behaviors and selecting the right I/O cache coherence method is essential. In this paper, we use Xilinx Zynq UltraScale+ as the SoC platform to show how certain I/O cache coherence method can perform better or worse in different situations, ultimately affecting the overall accelerator performances as well. Based on our analysis, we further explore possible software and hardware modifications to improve the I/O performances with different I/O cache coherence options. With our proposed modifications, the overall performance of SoC design can be averagely improved by 20%.

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Analysis and optimization of I/O cache coherency strategies for SoC-FPGA device

Abstract

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Keywords

ASJC Scopus subject areas

Online availability

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