Analysis and optimization of I/O cache coherency strategies for SoC-FPGA device

Seung Won Min, Sitao Huang, Mohamed El-Hadedy, Jinjun Xiong, Deming Chen, Wen Mei Hwu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Unlike traditional PCIe-based FPGA accelerators, heterogeneous SoC-FPGA devices provide tighter integrations between software running on CPUs and hardware accelerators. Modern heterogeneous SoC-FPGA platforms support multiple I/O cache coherence options between CPUs and FPGAs, but these options can have inadvertent effects on the achieved bandwidths depending on applications and data access patterns. To provide the most efficient communications between CPUs and accelerators, understanding the data transaction behaviors and selecting the right I/O cache coherence method is essential. In this paper, we use Xilinx Zynq UltraScale+ as the SoC platform to show how certain I/O cache coherence method can perform better or worse in different situations, ultimately affecting the overall accelerator performances as well. Based on our analysis, we further explore possible software and hardware modifications to improve the I/O performances with different I/O cache coherence options. With our proposed modifications, the overall performance of SoC design can be averagely improved by 20%.

Original languageEnglish (US)
Title of host publicationProceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019
EditorsIoannis Sourdis, Christos-Savvas Bouganis, Carlos Alvarez, Leonel Antonio Toledo Diaz, Pedro Valero, Xavier Martorell
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages301-306
Number of pages6
ISBN (Electronic)9781728148847
DOIs
StatePublished - Sep 2019
Event29th International Conferenceon Field-Programmable Logic and Applications, FPL 2019 - Barcelona, Spain
Duration: Sep 9 2019Sep 13 2019

Publication series

NameProceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019

Conference

Conference29th International Conferenceon Field-Programmable Logic and Applications, FPL 2019
CountrySpain
CityBarcelona
Period9/9/199/13/19

Keywords

  • Cache
  • Cache coherence
  • FPGA
  • Heterogenous computing

ASJC Scopus subject areas

  • Instrumentation
  • Artificial Intelligence
  • Computer Science Applications
  • Hardware and Architecture

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  • Cite this

    Min, S. W., Huang, S., El-Hadedy, M., Xiong, J., Chen, D., & Hwu, W. M. (2019). Analysis and optimization of I/O cache coherency strategies for SoC-FPGA device. In I. Sourdis, C-S. Bouganis, C. Alvarez, L. A. Toledo Diaz, P. Valero, & X. Martorell (Eds.), Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019 (pp. 301-306). [8892094] (Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/FPL.2019.00055