TY - JOUR
T1 - Analysis and design techniques for supply-noise mitigation in phase-locked loops
AU - Arakali, Abhijith
AU - Gondi, Srikanth
AU - Hanumolu, Pavan Kumar
N1 - Funding Information:
Manuscript received February 17, 2010; revised April 30, 2010; accepted May 13, 2010. Date of publication July 23, 2010; date of current version November 10, 2010. This work was supported in part by Intel and in part by SRC under Contract 2007-HJ-1597. This paper was recommended by Associate Editor H. Luong. A. Arakali is with the Silicon Laboratories, Inc., Broadcast Division, Sunny-vale, CA 94085 USA (e-mail: [email protected]). S. Gondi is with the GigFire Microsystems, Inc., San Jose, CA 95126 USA. P. K. Hanumolu is with the School of EECS, Oregon State University, Corvallis, OR 97331 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCSI.2010.2052507
PY - 2010
Y1 - 2010
N2 - Supply noise affects the jitter performance of ring oscillator-based phase-locked loops (PLLs) significantly. While the focus of much of the prior art is on supply noise in oscillators, this paper illustrates that supply noise in other building blocks also contribute significantly to PLL output jitter. Analytical expressions for supply-noise sensitivities are derived for each of the circuit blocks used in the PLL and insight into the mechanism through which supply noise appears at the PLL output is provided. Efficient supply-regulation schemes that combine a split-tuned PLL architecture with an optimized low-dropout regulator to achieve better than -22 dB of worst case supply-noise sensitivity for the whole PLL are presented. Fabricated in a 0.18 μM digital CMOS process, the prototype PLL occupies an area of 0.18 μm and operates from a 1.8 V supply. At 1.5 GHz, the total power consumption is 3.3 mW, of which 0.54 mW is consumed in the regulators. The measured output peak-to-peak jitter is 33 ps and 41 ps with no supply noise and with a 100-mV amplitude supply noise tone injected at the worst case noise frequency, respectively.
AB - Supply noise affects the jitter performance of ring oscillator-based phase-locked loops (PLLs) significantly. While the focus of much of the prior art is on supply noise in oscillators, this paper illustrates that supply noise in other building blocks also contribute significantly to PLL output jitter. Analytical expressions for supply-noise sensitivities are derived for each of the circuit blocks used in the PLL and insight into the mechanism through which supply noise appears at the PLL output is provided. Efficient supply-regulation schemes that combine a split-tuned PLL architecture with an optimized low-dropout regulator to achieve better than -22 dB of worst case supply-noise sensitivity for the whole PLL are presented. Fabricated in a 0.18 μM digital CMOS process, the prototype PLL occupies an area of 0.18 μm and operates from a 1.8 V supply. At 1.5 GHz, the total power consumption is 3.3 mW, of which 0.54 mW is consumed in the regulators. The measured output peak-to-peak jitter is 33 ps and 41 ps with no supply noise and with a 100-mV amplitude supply noise tone injected at the worst case noise frequency, respectively.
KW - Charge pump
KW - VCO buffer
KW - frequency divider
KW - loop filter
KW - phase-frequency detector
KW - phase-locked loops
KW - supply noise
KW - voltage regulator
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U2 - 10.1109/TCSI.2010.2052507
DO - 10.1109/TCSI.2010.2052507
M3 - Article
AN - SCOPUS:78149468450
SN - 1549-8328
VL - 57
SP - 2880
EP - 2889
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 11
M1 - 5518351
ER -