Analysis and design techniques for supply-noise mitigation in phase-locked loops

Abhijith Arakali, Srikanth Gondi, Pavan Kumar Hanumolu

Research output: Contribution to journalArticlepeer-review

Abstract

Supply noise affects the jitter performance of ring oscillator-based phase-locked loops (PLLs) significantly. While the focus of much of the prior art is on supply noise in oscillators, this paper illustrates that supply noise in other building blocks also contribute significantly to PLL output jitter. Analytical expressions for supply-noise sensitivities are derived for each of the circuit blocks used in the PLL and insight into the mechanism through which supply noise appears at the PLL output is provided. Efficient supply-regulation schemes that combine a split-tuned PLL architecture with an optimized low-dropout regulator to achieve better than -22 dB of worst case supply-noise sensitivity for the whole PLL are presented. Fabricated in a 0.18 μM digital CMOS process, the prototype PLL occupies an area of 0.18 μm and operates from a 1.8 V supply. At 1.5 GHz, the total power consumption is 3.3 mW, of which 0.54 mW is consumed in the regulators. The measured output peak-to-peak jitter is 33 ps and 41 ps with no supply noise and with a 100-mV amplitude supply noise tone injected at the worst case noise frequency, respectively.

Original languageEnglish (US)
Article number5518351
Pages (from-to)2880-2889
Number of pages10
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume57
Issue number11
DOIs
StatePublished - 2010
Externally publishedYes

Keywords

  • Charge pump
  • VCO buffer
  • frequency divider
  • loop filter
  • phase-frequency detector
  • phase-locked loops
  • supply noise
  • voltage regulator

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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