TY - JOUR
T1 - Analysis and Design of Integrated Voltage Regulators for Supply Noise Rejection during System-Level ESD
AU - Xiu, Yang
AU - Rosenbaum, Elyse
N1 - Manuscript received November 25, 2019; revised May 3, 2020; accepted June 17, 2020. Date of publication July 1, 2020; date of current version December 1, 2020. This work was supported by the Semiconductor Research Corporation (SRC) through the University of Texas at Dallas’ Texas Analog Center of Excellence (TxACE) under Grant 2810.005. This article was recommended by Associate Editor D. Zhao. (Corresponding author: Yang Xiu.) Yang Xiu was with the Department of Electrical and Computer Engineering, University of Illinois at Urbana–Champaign, Urbana, IL 61801 USA. She is now with Texas Instruments Incorporated, Dallas, TX 75243 USA (e-mail: [email protected]).
This work was supported by the Semiconductor Research Corporation (SRC) through the University of Texas at Dallas' Texas Analog Center of Excellence (TxACE) under Grant 2810.005.
PY - 2020/12
Y1 - 2020/12
N2 - This work studies the effect of system-level ESD on chip-level power integrity of ICs. The analysis reveals that isolating the ground nets of the various on-chip power domains impedes the cross-domain propagation of ESD-induced supply noise. Further analysis as well as circuit simulation show that an integrated voltage regulator (IVR) can provide increased immunity to ESD-induced supply noise, especially if the internally generated power supply does not utilize any PCB-level decoupling capacitors. However, the IVR's PMOS pass transistor may discharge the internally regulated supply if the IO supply domain collapses due to ESD. Key findings of the analysis are confirmed by measurements performed on two test chips which have differing IVR designs.
AB - This work studies the effect of system-level ESD on chip-level power integrity of ICs. The analysis reveals that isolating the ground nets of the various on-chip power domains impedes the cross-domain propagation of ESD-induced supply noise. Further analysis as well as circuit simulation show that an integrated voltage regulator (IVR) can provide increased immunity to ESD-induced supply noise, especially if the internally generated power supply does not utilize any PCB-level decoupling capacitors. However, the IVR's PMOS pass transistor may discharge the internally regulated supply if the IO supply domain collapses due to ESD. Key findings of the analysis are confirmed by measurements performed on two test chips which have differing IVR designs.
KW - System-level ESD
KW - integrated voltage regulator
KW - power integrity
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U2 - 10.1109/TCSI.2020.3004818
DO - 10.1109/TCSI.2020.3004818
M3 - Article
AN - SCOPUS:85097342781
SN - 1549-8328
VL - 67
SP - 4199
EP - 4210
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 12
M1 - 9130753
ER -