TY - GEN
T1 - An optimal algorithm for floorplan area optimization
AU - Wang, Ting Chi
AU - Wong, D. F.
PY - 1990
Y1 - 1990
N2 - An optimal algorithm for the VLSI floorplan area optimization problem is presented. The algorithm is an extension of the technique described by L. Stockmeyer (Information and Control, Vol. 59, pp. 91-101, 1983). Experimental results indicate that this algorithm pruned a very large number of redundant implementations. In addition, since the algorithm basically exploits the geometric property of the topology of the given floorplan, it does not need to depend on the polar dual graphs to calculate the longest paths. Consequently, it is able to run more efficiently than the branch-and-bound algorithm.
AB - An optimal algorithm for the VLSI floorplan area optimization problem is presented. The algorithm is an extension of the technique described by L. Stockmeyer (Information and Control, Vol. 59, pp. 91-101, 1983). Experimental results indicate that this algorithm pruned a very large number of redundant implementations. In addition, since the algorithm basically exploits the geometric property of the topology of the given floorplan, it does not need to depend on the polar dual graphs to calculate the longest paths. Consequently, it is able to run more efficiently than the branch-and-bound algorithm.
UR - http://www.scopus.com/inward/record.url?scp=0025546584&partnerID=8YFLogxK
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U2 - 10.1145/123186.123253
DO - 10.1145/123186.123253
M3 - Conference contribution
AN - SCOPUS:0025546584
SN - 081869650X
T3 - 27th ACM/IEEE Design Automation Conference. Proceedings 1990
SP - 180
EP - 186
BT - 27th ACM/IEEE Design Automation Conference. Proceedings 1990
PB - Publ by IEEE
T2 - 27th ACM/IEEE Design Automation Conference
Y2 - 24 June 1990 through 28 June 1990
ER -