An optimal algorithm for the VLSI floorplan area optimization problem is presented. The algorithm is an extension of the technique described by L. Stockmeyer (Information and Control, Vol. 59, pp. 91-101, 1983). Experimental results indicate that this algorithm pruned a very large number of redundant implementations. In addition, since the algorithm basically exploits the geometric property of the topology of the given floorplan, it does not need to depend on the polar dual graphs to calculate the longest paths. Consequently, it is able to run more efficiently than the branch-and-bound algorithm.