An MRAM-based deep in-memory architecture for deep neural networks

Ameya D. Patil; Haocheng Hua; Sujan Gonugondla; Mingu Kang; Naresh R. Shanbhag

doi:10.1109/ISCAS.2019.8702206

An MRAM-based deep in-memory architecture for deep neural networks

Ameya D. Patil, Haocheng Hua, Sujan Gonugondla, Mingu Kang, Naresh R. Shanbhag

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents an MRAM-based deep in-memory architecture (MRAM-DIMA) to efficiently implement multi-bit matrix vector multiplication for deep neural networks using a standard MRAM bitcell array. The MRAM-DIMA achieves an 4.5× and 70× lower energy and delay, respectively, compared to a conventional digital MRAM architecture. Behavioral models are developed to estimate the impact of circuit non-idealities, including process variations, on the DNN accuracy. An accuracy drop of ≤ 0.5% (≤ 1%) is observed for LeNet-300-100 on the MNIST dataset (a 9-layer CNN on the CIFAR-10 dataset), while tolerating 24% (12%) variation in cell conductance in a commercial 22 nm CMOS-MRAM process.

Original language	English (US)
Title of host publication	2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728103976
DOIs	https://doi.org/10.1109/ISCAS.2019.8702206
State	Published - 2019
Event	2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Sapporo, Japan Duration: May 26 2019 → May 29 2019

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2019-May
ISSN (Print)	0271-4310

Conference

Conference	2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019
Country/Territory	Japan
City	Sapporo
Period	5/26/19 → 5/29/19

ASJC Scopus subject areas

Electrical and Electronic Engineering

Online availability

10.1109/ISCAS.2019.8702206

Library availability

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Patil, A. D., Hua, H., Gonugondla, S., Kang, M., & Shanbhag, N. R. (2019). An MRAM-based deep in-memory architecture for deep neural networks. In 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings Article 8702206 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2019-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2019.8702206

An MRAM-based deep in-memory architecture for deep neural networks. / Patil, Ameya D.; Hua, Haocheng; Gonugondla, Sujan et al.
2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. 8702206 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2019-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Patil, AD, Hua, H, Gonugondla, S, Kang, M & Shanbhag, NR 2019, An MRAM-based deep in-memory architecture for deep neural networks. in 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings., 8702206, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2019-May, Institute of Electrical and Electronics Engineers Inc., 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, 5/26/19. https://doi.org/10.1109/ISCAS.2019.8702206

Patil AD, Hua H, Gonugondla S, Kang M, Shanbhag NR. An MRAM-based deep in-memory architecture for deep neural networks. In 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2019. 8702206. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS.2019.8702206

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title = "An MRAM-based deep in-memory architecture for deep neural networks",

abstract = "This paper presents an MRAM-based deep in-memory architecture (MRAM-DIMA) to efficiently implement multi-bit matrix vector multiplication for deep neural networks using a standard MRAM bitcell array. The MRAM-DIMA achieves an 4.5× and 70× lower energy and delay, respectively, compared to a conventional digital MRAM architecture. Behavioral models are developed to estimate the impact of circuit non-idealities, including process variations, on the DNN accuracy. An accuracy drop of ≤ 0.5% (≤ 1%) is observed for LeNet-300-100 on the MNIST dataset (a 9-layer CNN on the CIFAR-10 dataset), while tolerating 24% (12%) variation in cell conductance in a commercial 22 nm CMOS-MRAM process.",

author = "Patil, {Ameya D.} and Haocheng Hua and Sujan Gonugondla and Mingu Kang and Shanbhag, {Naresh R.}",

note = "Funding Information: This work was supported by DARPA FRANC Program. Publisher Copyright: {\textcopyright} 2019 IEEE; 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 ; Conference date: 26-05-2019 Through 29-05-2019",

year = "2019",

doi = "10.1109/ISCAS.2019.8702206",

language = "English (US)",

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An MRAM-based deep in-memory architecture for deep neural networks

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