An Improved Systolic Architecture for 2-D Digital Filters

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Abstract

An improved systolic architecture for two-dimensional infinite-impulse-response (HR) and finite-impulse-response (FIR) digital filters is presented. Comparisons with recently published work [2], [3] are made. When compared with the architecture in [2], a substantial reduction in the number of delay elements is observed. This reduction is of the order of 102 for a 2-D IIR filter and equals N + 1 for an Nth order 2-D FIR filter. The clock period has been made independent of the order of the filter. The speedup factor is the maximum achievable and is independent of the filter order. Comparison with [3] shows an improvement in the latency of the systolic array, which has been reduced from 1 to 0. A reduction of N + 1 delay elements has been achieved for the FIR filter. An error analysis for the new architecture is made, while error expressions for the architectures in [2], [3] are also presented.

Original languageEnglish (US)
Pages (from-to)1195-1202
Number of pages8
JournalIEEE Transactions on Signal Processing
Volume39
Issue number5
DOIs
StatePublished - May 1991
Externally publishedYes

ASJC Scopus subject areas

  • Signal Processing
  • Electrical and Electronic Engineering

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