Abstract
We present a new dual-loop frequency synthesizer for 5GHz wireless local-area network (WLAN) applications. In line with the IEEE 802.11a standard, the output frequency is targeted at 5.15G to 5.35GHz, with a frequency step of 5MHz. To make the use of ring-type VCO feasible for this application, we adopted a dual-loop frequency synthesizer architecture similar to [1]. However, it is critical that the primary loop of such a dual-loop frequency synthesizer is supported by a lownoise reference (by the peripheral loop). To address this problem, we propose a new fractional frequency multiplying delay-locked loop (FMDLL) working as the peripheral loop. MATLAB simulation results demonstrate the phase noise improvement by the use of the proposed FMDLL compared to the conventional design.
Original language | English (US) |
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Article number | 1465504 |
Pages (from-to) | 3986-3989 |
Number of pages | 4 |
Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
DOIs | |
State | Published - 2005 |
Externally published | Yes |
Event | IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan Duration: May 23 2005 → May 26 2005 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering