An Experimental Single-Chip Data Flow CPU

Gregory A. Uvieghara, Wen mei W. Hwu, Yoshinobu Nakagome, Deog Kyoon Jeong, David A. Hodges, Yale N. Patt, David D. Lee

Research output: Contribution to journalArticlepeer-review


HPSm thieh-nerformance substrate) is a single-chin data flow CPU [1], [2]. It enhances throughput by using three function units (two ALU’s and one memory interface) to exploit parallelism, while executing RISC instructions in a data-driven manner to keep the function units busy. HPSm is data driven in the sense that instructions whose operands are not ready are not permitted to stall the machine by blocking subsequent ones. In other words, an instruction whose operands are available can be executed out of order, regardless of its position in the instruction stream, if previous instructions are not ready for execution. In addition, it achieves an additional speedup by employing branch prediction to exploit concurrency between blocks of code. By using three function units, it is capable of operating at a peak performance of 30 MIPS while running at only 10 MHz. HPSm reduces the disparity between the sustained and the peak performances by the out-of-order execution of instructions on the three function units. It employs four on-chip smart memories to control the data-driven execution on the three function units, and to support branch prediction and exception handling [3]. Simulations indicate that HPSm achieves significant speedup over a single-chip RISC microarchitecture—-the Berkeley SPUR—which is implemented with the same fabrication technology and clock cycle. The HPSm chip has been designed for a 1.6-μm double-metal scalable CMOS process. It contains 87 279 transistors, occupies an area of 13.83 mm x 13.04 mm, and is estimated to dissipate 2 W at 10 MHz.

Original languageEnglish (US)
Pages (from-to)17-28
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Issue number1
StatePublished - Jan 1992

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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