An experimental single-chip data flow CPU

G. A. Uvieghara, Wen-Mei W Hwu, Y. Nakagome, D. K. Jeong, D. Lee, D. A. Hodges, Y. Patt

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The HPSm (high-performance substrate) single-chip data flow CPU is described. It enhances throughput by using three function units--two arithmetic and logic units (ALUs) and one memory interface--to exploit parallelism, while executing reduced instruction set computer (RISC) instructions in a data-driven manner to keep the function units busy. By using three function units, it is capable of operating at a peak performance of 30 MIPs while running at 10 MHz. It employs four on-chip smart memories to control data-driven execution on the three function units and to support branch prediction and exception handling. It is implemented in a 1.6-μm double-metal CMOS process. The chip contains 87,279 transistors, occupies an area of 13.83 mm × 13.04 mm, and dissipates 2 W.

Original languageEnglish (US)
Title of host publication90 Symp VLSI Circuits
PublisherPubl by IEEE
Pages119-120
Number of pages2
StatePublished - 1990
Externally publishedYes
Event1990 Symposium on VLSI Circuits - Honolulu, HI, USA
Duration: Jun 7 1990Jun 9 1990

Other

Other1990 Symposium on VLSI Circuits
CityHonolulu, HI, USA
Period6/7/906/9/90

ASJC Scopus subject areas

  • Engineering(all)

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