An experimental single-chip data flow CPU

G. A. Uvieghara, Wen-Mei W Hwu, Y. Nakagome, D. K. Jeong, D. Lee, D. A. Hodges, Y. Patt

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The HPSm (high-performance substrate) single-chip data flow CPU is described. It enhances throughput by using three function units--two arithmetic and logic units (ALUs) and one memory interface--to exploit parallelism, while executing reduced instruction set computer (RISC) instructions in a data-driven manner to keep the function units busy. By using three function units, it is capable of operating at a peak performance of 30 MIPs while running at 10 MHz. It employs four on-chip smart memories to control data-driven execution on the three function units and to support branch prediction and exception handling. It is implemented in a 1.6-μm double-metal CMOS process. The chip contains 87,279 transistors, occupies an area of 13.83 mm × 13.04 mm, and dissipates 2 W.

Original languageEnglish (US)
Title of host publication90 Symp VLSI Circuits
PublisherPubl by IEEE
Pages119-120
Number of pages2
StatePublished - 1990
Externally publishedYes
Event1990 Symposium on VLSI Circuits - Honolulu, HI, USA
Duration: Jun 7 1990Jun 9 1990

Other

Other1990 Symposium on VLSI Circuits
CityHonolulu, HI, USA
Period6/7/906/9/90

Fingerprint

Program processors
Data storage equipment
Interfaces (computer)
Transistors
Throughput
Substrates
Metals

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Uvieghara, G. A., Hwu, W-M. W., Nakagome, Y., Jeong, D. K., Lee, D., Hodges, D. A., & Patt, Y. (1990). An experimental single-chip data flow CPU. In 90 Symp VLSI Circuits (pp. 119-120). Publ by IEEE.

An experimental single-chip data flow CPU. / Uvieghara, G. A.; Hwu, Wen-Mei W; Nakagome, Y.; Jeong, D. K.; Lee, D.; Hodges, D. A.; Patt, Y.

90 Symp VLSI Circuits. Publ by IEEE, 1990. p. 119-120.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Uvieghara, GA, Hwu, W-MW, Nakagome, Y, Jeong, DK, Lee, D, Hodges, DA & Patt, Y 1990, An experimental single-chip data flow CPU. in 90 Symp VLSI Circuits. Publ by IEEE, pp. 119-120, 1990 Symposium on VLSI Circuits, Honolulu, HI, USA, 6/7/90.
Uvieghara GA, Hwu W-MW, Nakagome Y, Jeong DK, Lee D, Hodges DA et al. An experimental single-chip data flow CPU. In 90 Symp VLSI Circuits. Publ by IEEE. 1990. p. 119-120
Uvieghara, G. A. ; Hwu, Wen-Mei W ; Nakagome, Y. ; Jeong, D. K. ; Lee, D. ; Hodges, D. A. ; Patt, Y. / An experimental single-chip data flow CPU. 90 Symp VLSI Circuits. Publ by IEEE, 1990. pp. 119-120
@inproceedings{dc3f92557ea744cab01ec29afbaba673,
title = "An experimental single-chip data flow CPU",
abstract = "The HPSm (high-performance substrate) single-chip data flow CPU is described. It enhances throughput by using three function units--two arithmetic and logic units (ALUs) and one memory interface--to exploit parallelism, while executing reduced instruction set computer (RISC) instructions in a data-driven manner to keep the function units busy. By using three function units, it is capable of operating at a peak performance of 30 MIPs while running at 10 MHz. It employs four on-chip smart memories to control data-driven execution on the three function units and to support branch prediction and exception handling. It is implemented in a 1.6-μm double-metal CMOS process. The chip contains 87,279 transistors, occupies an area of 13.83 mm × 13.04 mm, and dissipates 2 W.",
author = "Uvieghara, {G. A.} and Hwu, {Wen-Mei W} and Y. Nakagome and Jeong, {D. K.} and D. Lee and Hodges, {D. A.} and Y. Patt",
year = "1990",
language = "English (US)",
pages = "119--120",
booktitle = "90 Symp VLSI Circuits",
publisher = "Publ by IEEE",

}

TY - GEN

T1 - An experimental single-chip data flow CPU

AU - Uvieghara, G. A.

AU - Hwu, Wen-Mei W

AU - Nakagome, Y.

AU - Jeong, D. K.

AU - Lee, D.

AU - Hodges, D. A.

AU - Patt, Y.

PY - 1990

Y1 - 1990

N2 - The HPSm (high-performance substrate) single-chip data flow CPU is described. It enhances throughput by using three function units--two arithmetic and logic units (ALUs) and one memory interface--to exploit parallelism, while executing reduced instruction set computer (RISC) instructions in a data-driven manner to keep the function units busy. By using three function units, it is capable of operating at a peak performance of 30 MIPs while running at 10 MHz. It employs four on-chip smart memories to control data-driven execution on the three function units and to support branch prediction and exception handling. It is implemented in a 1.6-μm double-metal CMOS process. The chip contains 87,279 transistors, occupies an area of 13.83 mm × 13.04 mm, and dissipates 2 W.

AB - The HPSm (high-performance substrate) single-chip data flow CPU is described. It enhances throughput by using three function units--two arithmetic and logic units (ALUs) and one memory interface--to exploit parallelism, while executing reduced instruction set computer (RISC) instructions in a data-driven manner to keep the function units busy. By using three function units, it is capable of operating at a peak performance of 30 MIPs while running at 10 MHz. It employs four on-chip smart memories to control data-driven execution on the three function units and to support branch prediction and exception handling. It is implemented in a 1.6-μm double-metal CMOS process. The chip contains 87,279 transistors, occupies an area of 13.83 mm × 13.04 mm, and dissipates 2 W.

UR - http://www.scopus.com/inward/record.url?scp=0025568306&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0025568306&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0025568306

SP - 119

EP - 120

BT - 90 Symp VLSI Circuits

PB - Publ by IEEE

ER -