An enhanced bottom-up algorithm for floorplan design

Thomas R. Mueller, D. F. Wong, C. L. Liu

Research output: Contribution to journalArticlepeer-review

Abstract

We describe in this paper a fast algorithm for the design of floorplans. The algorithm can be used to carry out the complete design of a floorplan or to improve an existing floorplan. It is based on an enhanced bottom-up iterative improvement technique, and is capable of obtaining good solutions with an increase in speed of approximately two orders of magnitude over an algorithm using the method of simulated annealing.

Original languageEnglish (US)
Pages (from-to)189-201
Number of pages13
JournalIntegration, the VLSI Journal
Volume7
Issue number2
DOIs
StatePublished - Aug 1989
Externally publishedYes

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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