An energy-efficient ECG processor in 45-nm CMOS using statistical error compensation

Rami A. Abdallah; Naresh R. Shanbhag

doi:10.1109/JSSC.2013.2280055

An energy-efficient ECG processor in 45-nm CMOS using statistical error compensation

Research output: Contribution to journal › Article › peer-review

Abstract

A subthreshold ECG processor in 45-nm IBM SOI CMOS is designed to operate at the minimum energy operating point (MEOP). Statistical error compensation (SEC) is employed to further reduce energy (E-{\min}) at the MEOP. SEC is shown to reduce E_\min by 28% compared with the conventional (error-free) case while maintaining acceptable beat-detection performance. SEC enables the supply voltage to be scaled to 15% below its critical value at MEOP, while compensating for a 58% precorrection error rate p_e. These results represent an improvement of 19× in beat-detection performance and 600× in p_e over conventional (error-free) systems. The prototype IC consumes 14.5 fJ/cycle/1k-gate and exhibits 4.7× better energy efficiency than the state of the art while tolerating 16× more voltage variations.

Original language	English (US)
Article number	6600915
Pages (from-to)	2882-2893
Number of pages	12
Journal	IEEE Journal of Solid-State Circuits
Volume	48
Issue number	11
DOIs	https://doi.org/10.1109/JSSC.2013.2280055
State	Published - 2013

Keywords

Error resiliency
robust design
statistical computing
subthreshold
ultralow power
voltage overscaling

ASJC Scopus subject areas

Electrical and Electronic Engineering

Online availability

10.1109/JSSC.2013.2280055

Library availability

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abstract = "A subthreshold ECG processor in 45-nm IBM SOI CMOS is designed to operate at the minimum energy operating point (MEOP). Statistical error compensation (SEC) is employed to further reduce energy (E-{\min}) at the MEOP. SEC is shown to reduce E\min by 28% compared with the conventional (error-free) case while maintaining acceptable beat-detection performance. SEC enables the supply voltage to be scaled to 15% below its critical value at MEOP, while compensating for a 58% precorrection error rate pe. These results represent an improvement of 19× in beat-detection performance and 600× in pe over conventional (error-free) systems. The prototype IC consumes 14.5 fJ/cycle/1k-gate and exhibits 4.7× better energy efficiency than the state of the art while tolerating 16× more voltage variations.",

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An energy-efficient ECG processor in 45-nm CMOS using statistical error compensation

Abstract

Keywords

ASJC Scopus subject areas

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