TY - GEN
T1 - An energy-efficient classifier via boosted spin channel networks
AU - Patil, Ameya D.
AU - Manipatruni, Sasikanth
AU - Nikonov, Dmitri
AU - Young, Ian A.
AU - Shanbhag, Naresh R.
N1 - Funding Information:
This work was supported in part by C-BRIC, one of six centers in JUMP, a Semiconductor Research Corporation (SRC) program sponsored by DARPA, and SONIC, one of the six SRC STARnet Centers sponsored by MARCO and DARPA.
Publisher Copyright:
© 2019 IEEE
PY - 2019
Y1 - 2019
N2 - With diminishing energy and delay benefits via CMOS scaling, there is much interest in exploring the use of alternative state variables such as electronic spin. Multiple research efforts are underway exploring both Boolean and non-Boolean design space using spin devices in order to make their energy and delay benefits competitive to CMOS. In this paper, we propose spin channel networks (SCNs) - spin-based circuits that exploit exponential decay of spin current to efficiently realize multi-bit dot product computation. We show that proposed SCNs can be employed with adaptive boosting (AdaBoost) learning algorithm to efficiently realize a binary classifier for breast cancer detection. The proposed SCN implementation achieves 112× and 14× lower energy per decision compared to the conventional all spin logic (ASL) and 20 nm CMOS designs, respectively, for identical decision throughput.
AB - With diminishing energy and delay benefits via CMOS scaling, there is much interest in exploring the use of alternative state variables such as electronic spin. Multiple research efforts are underway exploring both Boolean and non-Boolean design space using spin devices in order to make their energy and delay benefits competitive to CMOS. In this paper, we propose spin channel networks (SCNs) - spin-based circuits that exploit exponential decay of spin current to efficiently realize multi-bit dot product computation. We show that proposed SCNs can be employed with adaptive boosting (AdaBoost) learning algorithm to efficiently realize a binary classifier for breast cancer detection. The proposed SCN implementation achieves 112× and 14× lower energy per decision compared to the conventional all spin logic (ASL) and 20 nm CMOS designs, respectively, for identical decision throughput.
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U2 - 10.1109/ISCAS.2019.8702648
DO - 10.1109/ISCAS.2019.8702648
M3 - Conference contribution
AN - SCOPUS:85066784850
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019
Y2 - 26 May 2019 through 29 May 2019
ER -