Abstract
With diminishing energy and delay benefits via CMOS scaling, there is much interest in exploring the use of alternative state variables such as electronic spin. Multiple research efforts are underway exploring both Boolean and non-Boolean design space using spin devices in order to make their energy and delay benefits competitive to CMOS. In this paper, we propose spin channel networks (SCNs) - spin-based circuits that exploit exponential decay of spin current to efficiently realize multi-bit dot product computation. We show that proposed SCNs can be employed with adaptive boosting (AdaBoost) learning algorithm to efficiently realize a binary classifier for breast cancer detection. The proposed SCN implementation achieves 112× and 14× lower energy per decision compared to the conventional all spin logic (ASL) and 20 nm CMOS designs, respectively, for identical decision throughput.
| Original language | English (US) |
|---|---|
| Title of host publication | 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9781728103976 |
| DOIs | |
| State | Published - Jan 1 2019 |
| Event | 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Sapporo, Japan Duration: May 26 2019 → May 29 2019 |
Publication series
| Name | Proceedings - IEEE International Symposium on Circuits and Systems |
|---|---|
| Volume | 2019-May |
| ISSN (Print) | 0271-4310 |
Conference
| Conference | 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 |
|---|---|
| Country | Japan |
| City | Sapporo |
| Period | 5/26/19 → 5/29/19 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
An energy-efficient classifier via boosted spin channel networks. / Patil, Ameya D.; Manipatruni, Sasikanth; Nikonov, Dmitri; Young, Ian A.; Shanbhag, Naresh R.
2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. 8702648 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2019-May).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - An energy-efficient classifier via boosted spin channel networks
AU - Patil, Ameya D.
AU - Manipatruni, Sasikanth
AU - Nikonov, Dmitri
AU - Young, Ian A.
AU - Shanbhag, Naresh R
PY - 2019/1/1
Y1 - 2019/1/1
N2 - With diminishing energy and delay benefits via CMOS scaling, there is much interest in exploring the use of alternative state variables such as electronic spin. Multiple research efforts are underway exploring both Boolean and non-Boolean design space using spin devices in order to make their energy and delay benefits competitive to CMOS. In this paper, we propose spin channel networks (SCNs) - spin-based circuits that exploit exponential decay of spin current to efficiently realize multi-bit dot product computation. We show that proposed SCNs can be employed with adaptive boosting (AdaBoost) learning algorithm to efficiently realize a binary classifier for breast cancer detection. The proposed SCN implementation achieves 112× and 14× lower energy per decision compared to the conventional all spin logic (ASL) and 20 nm CMOS designs, respectively, for identical decision throughput.
AB - With diminishing energy and delay benefits via CMOS scaling, there is much interest in exploring the use of alternative state variables such as electronic spin. Multiple research efforts are underway exploring both Boolean and non-Boolean design space using spin devices in order to make their energy and delay benefits competitive to CMOS. In this paper, we propose spin channel networks (SCNs) - spin-based circuits that exploit exponential decay of spin current to efficiently realize multi-bit dot product computation. We show that proposed SCNs can be employed with adaptive boosting (AdaBoost) learning algorithm to efficiently realize a binary classifier for breast cancer detection. The proposed SCN implementation achieves 112× and 14× lower energy per decision compared to the conventional all spin logic (ASL) and 20 nm CMOS designs, respectively, for identical decision throughput.
UR - http://www.scopus.com/inward/record.url?scp=85066784850&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85066784850&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2019.8702648
DO - 10.1109/ISCAS.2019.8702648
M3 - Conference contribution
AN - SCOPUS:85066784850
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
ER -