TY - JOUR
T1 - An ECO routing algorithm for eliminating coupling-capacitance violations
AU - Xiang, Hua
AU - Chao, Kai Yuan
AU - Wong, Martin D.F.
N1 - Funding Information:
Manuscript received October 22, 2004; revised February 27, 2005 and May 30, 2005. This work was supported in part by the National Science Foundation under Grant CCR-0306244. This paper was recommended by Associate Editor T. Yoshimura. H. Xiang is with the IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA (e-mail: [email protected]). K.-Y. Chao is with the Intel Corporation, Hillsboro, OR 97124 USA (e-mail: [email protected]). M. D. F. Wong is with the Electrical and Computer Engineering Department, University of Illinois, Urbana–Champaign, IL 61801 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/TCAD.2005.857396
PY - 2006/9
Y1 - 2006/9
N2 - Engineering change order changes are almost inevitable in the late stages of a design process. Based on an existing design, incremental change is favored since it can avoid considerable efforts of redoing the whole process and can minimize the disturbance on the existing converged design. The couplingcapacitance violation elimination (CVE) problem is addressed. Due to the changes in the multiple layer routing design, the total coupling capacitance on some signal wire segments on a layer may be larger than their allowable bounds after postlayout timing/noise analysis. The target is to find a new routing solution without coupling-capacitance violations under certain constraints, which helps to keep the new design close to the original one. This paper proposes a two-stage algorithm to solve CVE problems, and present optimization strategies to speed up the execution. Experimental results demonstrate the efficiency and effectiveness of this algorithm.
AB - Engineering change order changes are almost inevitable in the late stages of a design process. Based on an existing design, incremental change is favored since it can avoid considerable efforts of redoing the whole process and can minimize the disturbance on the existing converged design. The couplingcapacitance violation elimination (CVE) problem is addressed. Due to the changes in the multiple layer routing design, the total coupling capacitance on some signal wire segments on a layer may be larger than their allowable bounds after postlayout timing/noise analysis. The target is to find a new routing solution without coupling-capacitance violations under certain constraints, which helps to keep the new design close to the original one. This paper proposes a two-stage algorithm to solve CVE problems, and present optimization strategies to speed up the execution. Experimental results demonstrate the efficiency and effectiveness of this algorithm.
KW - Coupling capacitance
KW - Engineering change order (ECO)
KW - Routing
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U2 - 10.1109/TCAD.2005.857396
DO - 10.1109/TCAD.2005.857396
M3 - Article
AN - SCOPUS:33748114506
SN - 0278-0070
VL - 25
SP - 1754
EP - 1761
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 9
M1 - 1673749
ER -