In the deep submicron manufacturing (DSM) era, lithography/yield and noise are critical issues to be considered. Optical Proximity Correction (OPC) is becoming a key compensate technique for the light diffraction effect in lithography. Both OPC effect and the capacitive coupling on some wire segments can only be analyzed post routing in late design stage or post-silicon stepping design change. ECO (Engineering Change Orders) is used in late design stage to fix violations that exceed the given OPC and coupling capacitance thresholds derived from analysis. These violations must be corrected in order to guarantee performance and yield. In this paper, we propose the first ECO routing algorithm which eliminates both OPC and coupling capacitance violations for wires. At the same time, the ECO routing obeys the given constraints so as to keep the new routing solution close to the existing one to preserve design timing and layout convergence.