An Analytical Metal Resistance Model and Its Application for Sub-22-nm Metal-Gate CMOS

Xin Miao; Ruqiang Bao; Unoh Kwon; Keith Wong; Werner Rausch; Weihao Weng; Richard Wachnik; Stephan Grunow; Vijay Narayanan; Xiuling Li; Siddarth Krishnan

doi:10.1109/LED.2015.2404805

An Analytical Metal Resistance Model and Its Application for Sub-22-nm Metal-Gate CMOS

Xin Miao, Ruqiang Bao, Unoh Kwon, Keith Wong, Werner Rausch, Weihao Weng, Richard Wachnik, Stephan Grunow, Vijay Narayanan, Xiuling Li, Siddarth Krishnan

Research output: Contribution to journal › Article › peer-review

Abstract

Gate resistance, middle of line resistance, and back end of line resistance in modern metal-gate CMOS increase drastically as the dimensions of the gates, interconnects and vias scale down close to or below the bulk electron mean free paths (MFPs) of the metal materials. These resistances, especially the gate resistance, impose more and more significant RC delay to CMOS circuits and become significant concerns in sub-22-nm CMOS. In order to optimize the metal-gate materials and structures for low resistance, accurate metal resistance model is needed. In this letter, we propose an analytical metal resistance model applicable for metal wires and films even with sub-MFP sizes. Our model includes scattering effects from surfaces, interfaces, and grain boundaries, and has been successfully verified on W metal gates with the feature sizes ranging from 20 to 70 nm.

Original language	English (US)
Article number	7045484
Pages (from-to)	384-386
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	36
Issue number	4
DOIs	https://doi.org/10.1109/LED.2015.2404805
State	Published - Apr 1 2015

Keywords

CMOS
analytical model
gate resistance
metal gate
metal resistance
scattering

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Online availability

10.1109/LED.2015.2404805

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title = "An Analytical Metal Resistance Model and Its Application for Sub-22-nm Metal-Gate CMOS",

abstract = "Gate resistance, middle of line resistance, and back end of line resistance in modern metal-gate CMOS increase drastically as the dimensions of the gates, interconnects and vias scale down close to or below the bulk electron mean free paths (MFPs) of the metal materials. These resistances, especially the gate resistance, impose more and more significant RC delay to CMOS circuits and become significant concerns in sub-22-nm CMOS. In order to optimize the metal-gate materials and structures for low resistance, accurate metal resistance model is needed. In this letter, we propose an analytical metal resistance model applicable for metal wires and films even with sub-MFP sizes. Our model includes scattering effects from surfaces, interfaces, and grain boundaries, and has been successfully verified on W metal gates with the feature sizes ranging from 20 to 70 nm.",

keywords = "CMOS, analytical model, gate resistance, metal gate, metal resistance, scattering",

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AU - Miao, Xin

AU - Bao, Ruqiang

AU - Kwon, Unoh

AU - Wong, Keith

AU - Rausch, Werner

AU - Weng, Weihao

AU - Wachnik, Richard

AU - Grunow, Stephan

AU - Narayanan, Vijay

AU - Li, Xiuling

AU - Krishnan, Siddarth

PY - 2015/4/1

Y1 - 2015/4/1

N2 - Gate resistance, middle of line resistance, and back end of line resistance in modern metal-gate CMOS increase drastically as the dimensions of the gates, interconnects and vias scale down close to or below the bulk electron mean free paths (MFPs) of the metal materials. These resistances, especially the gate resistance, impose more and more significant RC delay to CMOS circuits and become significant concerns in sub-22-nm CMOS. In order to optimize the metal-gate materials and structures for low resistance, accurate metal resistance model is needed. In this letter, we propose an analytical metal resistance model applicable for metal wires and films even with sub-MFP sizes. Our model includes scattering effects from surfaces, interfaces, and grain boundaries, and has been successfully verified on W metal gates with the feature sizes ranging from 20 to 70 nm.

AB - Gate resistance, middle of line resistance, and back end of line resistance in modern metal-gate CMOS increase drastically as the dimensions of the gates, interconnects and vias scale down close to or below the bulk electron mean free paths (MFPs) of the metal materials. These resistances, especially the gate resistance, impose more and more significant RC delay to CMOS circuits and become significant concerns in sub-22-nm CMOS. In order to optimize the metal-gate materials and structures for low resistance, accurate metal resistance model is needed. In this letter, we propose an analytical metal resistance model applicable for metal wires and films even with sub-MFP sizes. Our model includes scattering effects from surfaces, interfaces, and grain boundaries, and has been successfully verified on W metal gates with the feature sizes ranging from 20 to 70 nm.

KW - CMOS

KW - analytical model

KW - gate resistance

KW - metal gate

KW - metal resistance

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An Analytical Metal Resistance Model and Its Application for Sub-22-nm Metal-Gate CMOS

Abstract

Keywords

ASJC Scopus subject areas

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