An analytical approach to scheduling code for superscalar and VLIW architectures

Shyh Kwei Chen, W. Fuchs, Wen-Mei W Hwu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Superscalar and Very Long Instruction Word (VLIW) architectures exploit fine-grain parallelism to achieve better performance. Static scheduling techniques, such as trace scheduling [1] and superblock scheduling [2], can effectively produce compact code for these architectures. In this paper, we present an analytical approach for bookkeeping in code scheduling that alleviates the coding complexity and instruction duplication limitations of the previous approaches. We describe techniques that allow instructions to be moved around loop and if-then-else constructs using global information. We also show that according to the classification of the register sets, certain instructions can be moved around subroutine calls, since their register live ranges can be predetermined across the procedural boundaries at compile time. Performance is compared with respect to the speed-up, the code size and the scheduling time. Experimental results indicate that the code growth and the speed-up are both improved with a small increase in scheduling time.

Original languageEnglish (US)
Title of host publicationProceedings of the 1994 International Conference on Parallel Processing, ICPP 1994
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)0849324939, 9780849324932
DOIs
StatePublished - Jan 1 1994
Event23rd International Conference on Parallel Processing, ICPP 1994 - Raleigh, NC, United States
Duration: Aug 15 1994Aug 19 1994

Publication series

NameProceedings of the International Conference on Parallel Processing
Volume1
ISSN (Print)0190-3918

Other

Other23rd International Conference on Parallel Processing, ICPP 1994
CountryUnited States
CityRaleigh, NC
Period8/15/948/19/94

Fingerprint

Very long instruction word architecture
Superscalar
Scheduling
Speedup
Subroutines
Duplication
Parallelism
Architecture
Coding
Trace
Experimental Results
Range of data

ASJC Scopus subject areas

  • Software
  • Mathematics(all)
  • Hardware and Architecture

Cite this

Chen, S. K., Fuchs, W., & Hwu, W-M. W. (1994). An analytical approach to scheduling code for superscalar and VLIW architectures. In Proceedings of the 1994 International Conference on Parallel Processing, ICPP 1994 [4115732] (Proceedings of the International Conference on Parallel Processing; Vol. 1). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICPP.1994.50

An analytical approach to scheduling code for superscalar and VLIW architectures. / Chen, Shyh Kwei; Fuchs, W.; Hwu, Wen-Mei W.

Proceedings of the 1994 International Conference on Parallel Processing, ICPP 1994. Institute of Electrical and Electronics Engineers Inc., 1994. 4115732 (Proceedings of the International Conference on Parallel Processing; Vol. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Chen, SK, Fuchs, W & Hwu, W-MW 1994, An analytical approach to scheduling code for superscalar and VLIW architectures. in Proceedings of the 1994 International Conference on Parallel Processing, ICPP 1994., 4115732, Proceedings of the International Conference on Parallel Processing, vol. 1, Institute of Electrical and Electronics Engineers Inc., 23rd International Conference on Parallel Processing, ICPP 1994, Raleigh, NC, United States, 8/15/94. https://doi.org/10.1109/ICPP.1994.50
Chen SK, Fuchs W, Hwu W-MW. An analytical approach to scheduling code for superscalar and VLIW architectures. In Proceedings of the 1994 International Conference on Parallel Processing, ICPP 1994. Institute of Electrical and Electronics Engineers Inc. 1994. 4115732. (Proceedings of the International Conference on Parallel Processing). https://doi.org/10.1109/ICPP.1994.50
Chen, Shyh Kwei ; Fuchs, W. ; Hwu, Wen-Mei W. / An analytical approach to scheduling code for superscalar and VLIW architectures. Proceedings of the 1994 International Conference on Parallel Processing, ICPP 1994. Institute of Electrical and Electronics Engineers Inc., 1994. (Proceedings of the International Conference on Parallel Processing).
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