@inproceedings{8d3c87645b5e49c3aef4912eca41e20d,
title = "An algorithm for integrated pin assignment and buffer planning",
abstract = "The buffer block methodology has become increasingly popular as more and more buffers are needed in deep-submicron design, and it leads to many challenging problems in physical design. In this paper, we present a polynomial-time exact algorithm for integrated pin assignment and buffer planning for all two-pin nets from one macro block (source block) to all other blocks of a given buffer block plan as well as minimizing the total cost α· W + β· R for any positive α and β where W is the total wire length and R is the number of buffers. By applying this algorithm iteratively (each time pick one block as the source block), it provides a polynomial-time algorithm for pin assignment and buffer planning for nets among multiple macro blocks. Experimental results demonstrate its efficiency and effectiveness.",
keywords = "Buffer insertion, Min-cost maximum flow, Pin assignment",
author = "Hua Xiang and Xiaoping Tang and Wong, {D. F.}",
year = "2002",
doi = "10.1145/513918.514067",
language = "English (US)",
isbn = "1581134614",
series = "Proceedings - Design Automation Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "584--589",
booktitle = "Proceedings of the 39th Annual Design Automation Conference, DAC'02",
address = "United States",
note = "39th Design Automation Conference ; Conference date: 10-06-2002 Through 14-06-2002",
}