TY - GEN
T1 - An 8mW 10b 50MS/s pipelined ADC using 25dB opamp
AU - Kim, Min Gyu
AU - Kratyuk, Volodymyr
AU - Hanumolu, Pavan Kumar
AU - Ahn, Gil Cho
AU - Kwon, Sunwoo
AU - Moon, Un Ku
PY - 2008
Y1 - 2008
N2 - A 10-bit 50MS/s pipelined ADC is presented. A 25dB open loop dc gain amplifier is employed in the MDAC operation. The low opamp dc gain in the extreme is tolerated due to the use of a reference scaling scheme in conjunction with a background offset calibration. An intermediate gain stage is inserted into the pipeline to compensate for the accumulated reduction of reference and signal swing. The prototype IC implemented in a 90nm CMOS process achieves -63.2dB THD, 48.8dB SNR, and 48.6dB SNDR, while consuming 8mW from a IV supply.
AB - A 10-bit 50MS/s pipelined ADC is presented. A 25dB open loop dc gain amplifier is employed in the MDAC operation. The low opamp dc gain in the extreme is tolerated due to the use of a reference scaling scheme in conjunction with a background offset calibration. An intermediate gain stage is inserted into the pipeline to compensate for the accumulated reduction of reference and signal swing. The prototype IC implemented in a 90nm CMOS process achieves -63.2dB THD, 48.8dB SNR, and 48.6dB SNDR, while consuming 8mW from a IV supply.
UR - http://www.scopus.com/inward/record.url?scp=67649989612&partnerID=8YFLogxK
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U2 - 10.1109/ASSCC.2008.4708726
DO - 10.1109/ASSCC.2008.4708726
M3 - Conference contribution
AN - SCOPUS:67649989612
SN - 9781424426058
T3 - Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
SP - 49
EP - 52
BT - Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
T2 - 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Y2 - 3 November 2008 through 5 November 2008
ER -