An 8Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation and clock deskew

James E. Jaussi, Ganesh Balamurugan, David R. Johnson, Bryan K. Casper, Aaron Martin, Joe T. Kennedy, Naresh R Shanbhag, Randy Mooney

Research output: Contribution to journalConference article

Abstract

A 8Gb/s binary source-synchronous I/O link with adaptive receiver-equalization, offset cancellation and clock deskew is implemented in 0.13μm CMOS. The analog equalizer is implemented as an 8-way interleaved. 4-tap discrete-time linear filter. On-die adaptation logic determines optimal receiver settings.

Original languageEnglish (US)
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume47
StatePublished - Jun 2 2004
EventDigest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference - San Francisco, CA., United States
Duration: Feb 15 2003Feb 19 2003

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Equalizers
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ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

An 8Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation and clock deskew. / Jaussi, James E.; Balamurugan, Ganesh; Johnson, David R.; Casper, Bryan K.; Martin, Aaron; Kennedy, Joe T.; Shanbhag, Naresh R; Mooney, Randy.

In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol. 47, 02.06.2004.

Research output: Contribution to journalConference article

Jaussi, James E. ; Balamurugan, Ganesh ; Johnson, David R. ; Casper, Bryan K. ; Martin, Aaron ; Kennedy, Joe T. ; Shanbhag, Naresh R ; Mooney, Randy. / An 8Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation and clock deskew. In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2004 ; Vol. 47.
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