An 8Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation and clock deskew

James E. Jaussi; Ganesh Balamurugan; David R. Johnson; Bryan K. Casper; Aaron Martin; Joe T. Kennedy; Naresh Shanbhag; Randy Mooney

An 8Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation and clock deskew

James E. Jaussi, Ganesh Balamurugan, David R. Johnson, Bryan K. Casper, Aaron Martin, Joe T. Kennedy, Naresh Shanbhag, Randy Mooney

Research output: Contribution to journal › Conference article › peer-review

Abstract

A 8Gb/s binary source-synchronous I/O link with adaptive receiver-equalization, offset cancellation and clock deskew is implemented in 0.13μm CMOS. The analog equalizer is implemented as an 8-way interleaved. 4-tap discrete-time linear filter. On-die adaptation logic determines optimal receiver settings.

Original language	English (US)
Pages (from-to)	246-247+231+525
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	47
State	Published - Jun 2 2004
Event	Digest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference - San Francisco, CA., United States Duration: Feb 15 2003 → Feb 19 2003

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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An 8Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation and clock deskew. / Jaussi, James E.; Balamurugan, Ganesh; Johnson, David R. et al.
In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol. 47, 02.06.2004, p. 246-247+231+525.

Research output: Contribution to journal › Conference article › peer-review

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AU - Shanbhag, Naresh

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An 8Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation and clock deskew

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