An 8Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation and clock deskew

James E. Jaussi, Ganesh Balamurugan, David R. Johnson, Bryan K. Casper, Aaron Martin, Joe T. Kennedy, Naresh Shanbhag, Randy Mooney

Research output: Contribution to journalConference article

Abstract

A 8Gb/s binary source-synchronous I/O link with adaptive receiver-equalization, offset cancellation and clock deskew is implemented in 0.13μm CMOS. The analog equalizer is implemented as an 8-way interleaved. 4-tap discrete-time linear filter. On-die adaptation logic determines optimal receiver settings.

Original languageEnglish (US)
Pages (from-to)246-247+231+525
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume47
StatePublished - Jun 2 2004
EventDigest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference - San Francisco, CA., United States
Duration: Feb 15 2003Feb 19 2003

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Jaussi, J. E., Balamurugan, G., Johnson, D. R., Casper, B. K., Martin, A., Kennedy, J. T., Shanbhag, N., & Mooney, R. (2004). An 8Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation and clock deskew. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 47, 246-247+231+525.