An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM with a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques

An 8.5-Gb/s/pin (Gb/s) 12-Gb LPDDR5 SDRAM is implemented in a second-generation 10-nm DRAM process with a hybrid-bank architecture that provides a power-optimized bank solution depending on the bank modes (4B/4BG, 16B-merged bank, 8B-split bank). Based on the specified bank modes, vertical and horizontal skew-cancel schemes for high density and an RBUS-based DBI ac to minimize data transition are newly proposed. Thus, the switching power of RBUS DBI ac is saved by 8.9% compared to that of DBI ac 'OFF.' To improve the rank interleaving efficiency with a current increase, partially enabled WCK (PE-WCK) mode is proposed, which minimizes the number of enabled circuits for maintaining the WCK2CK synchronization. Therefore, the current can be saved by 62% without a timing constraint compared to the WCK always-ON mode. To achieve high-speed operation beyond 6.4 Gb/s, speed-boosting techniques, namely, the two-step duty corrector, active resonant load (ARL), and one-tap decision feedback equalizer (DFE) with offset calibration, are newly adopted. In the coarse step in the two-step duty corrector, the value of the duty error decreases to below 5% by suppressing the dc signal. In the fine step, the remaining duty error is further reduced within 2.5 ps by the duty cycle monitor (DCM) and duty cycle adjustor (DCA). Moreover, the skew increase beyond 6.4 Gb/s due to the bandwidth limit by the heavy loading of four-phase WCK signals is alleviated by the ARL, where the four-phase skew is within 5 ps irrespective of process, voltage, and temperature (PVT) variations. The direct feedback DFE enables fast feedback (< 118 ps) for tap coefficient control, and offset calibration reduces the three-sigma offset of the four dynamic latches in DQ within 5 mV.