An 8.5-11.5-Gbps SONET transceiver with referenceless clock and data recovery (CDR) employing an algorithmic frequency acquisition scheme is presented. Without any training sequence, the frequency acquisition algorithm utilizes a modified digital quadricorrelator frequency detector (M-DQFD) incorporated into an LC-based VCO coarse tuning adjustment. M-DQFD eliminates the dead-zone problem associated with high dispersion and low SNR links. Fabricated in 65-nm CMOS process, the transceiver complies with stringent OC-192 jitter requirements. With a 400-μs acquisition time, the receiver achieves a high-frequency jitter tolerance of 0.58UIpp at 10-mVppd input sensitivity. The transmitter output exhibits a random jitter of 205fs rms. The transceiver occupies 0.97 mm2 and consumes 125 mA at 1.0-V supply voltage.
- Clock and data recovery (CDR)
- Digital quadricorrelator frequency detector (DQFD)
ASJC Scopus subject areas
- Electrical and Electronic Engineering