An 8×3.2Gb/s parallel receiver with collaborative timing recovery

Ankur Agrawal; Pavan Kumar Hanumolu; Gu Yeon Wei

doi:10.1109/ISSCC.2008.4523260

An 8×3.2Gb/s parallel receiver with collaborative timing recovery

Ankur Agrawal, Pavan Kumar Hanumolu, Gu Yeon Wei

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

An 8×3.2Gb/s parallel receiver with collaborative timing recovery is realized in a 0.13μm 1P8M CMOS logic process. A global timing-recovery block that combines timing-error information from several parallel data channels more than doubles the jitter tolerance bandwidth while consuming <6.4mW/Gb/s from a 1.1V supply.

Original language	English (US)
Title of host publication	2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC
Pages	468-469+628+451
DOIs	https://doi.org/10.1109/ISSCC.2008.4523260
State	Published - 2008
Externally published	Yes
Event	2008 IEEE International Solid State Circuits Conference, ISSCC - San Francisco, CA, United States Duration: Feb 3 2008 → Feb 7 2008

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	51
ISSN (Print)	0193-6530

Other

Other	2008 IEEE International Solid State Circuits Conference, ISSCC
Country	United States
City	San Francisco, CA
Period	2/3/08 → 2/7/08

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/ISSCC.2008.4523260

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Agrawal, A., Hanumolu, P. K., & Wei, G. Y. (2008). An 8×3.2Gb/s parallel receiver with collaborative timing recovery. In 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC (pp. 468-469+628+451). [4523260] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 51). https://doi.org/10.1109/ISSCC.2008.4523260

An 8×3.2Gb/s parallel receiver with collaborative timing recovery. / Agrawal, Ankur; Hanumolu, Pavan Kumar; Wei, Gu Yeon.

2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC. 2008. p. 468-469+628+451 4523260 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 51).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Agrawal, A, Hanumolu, PK & Wei, GY 2008, An 8×3.2Gb/s parallel receiver with collaborative timing recovery. in 2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC., 4523260, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 51, pp. 468-469+628+451, 2008 IEEE International Solid State Circuits Conference, ISSCC, San Francisco, CA, United States, 2/3/08. https://doi.org/10.1109/ISSCC.2008.4523260

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abstract = "An 8×3.2Gb/s parallel receiver with collaborative timing recovery is realized in a 0.13μm 1P8M CMOS logic process. A global timing-recovery block that combines timing-error information from several parallel data channels more than doubles the jitter tolerance bandwidth while consuming <6.4mW/Gb/s from a 1.1V supply.",

author = "Ankur Agrawal and Hanumolu, {Pavan Kumar} and Wei, {Gu Yeon}",

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An 8×3.2Gb/s parallel receiver with collaborative timing recovery

Abstract

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ASJC Scopus subject areas

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