An 8×3.2Gb/s parallel receiver with collaborative timing recovery

Ankur Agrawal, Pavan Kumar Hanumolu, Gu Yeon Wei

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

An 8×3.2Gb/s parallel receiver with collaborative timing recovery is realized in a 0.13μm 1P8M CMOS logic process. A global timing-recovery block that combines timing-error information from several parallel data channels more than doubles the jitter tolerance bandwidth while consuming <6.4mW/Gb/s from a 1.1V supply.

Original languageEnglish (US)
Title of host publication2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC
Pages468-469+628+451
DOIs
StatePublished - 2008
Externally publishedYes
Event2008 IEEE International Solid State Circuits Conference, ISSCC - San Francisco, CA, United States
Duration: Feb 3 2008Feb 7 2008

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume51
ISSN (Print)0193-6530

Other

Other2008 IEEE International Solid State Circuits Conference, ISSCC
CountryUnited States
CitySan Francisco, CA
Period2/3/082/7/08

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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