@inproceedings{ac4367c6ae9b47778ded0410c5656f28,
title = "An 8×3.2Gb/s parallel receiver with collaborative timing recovery",
abstract = "An 8×3.2Gb/s parallel receiver with collaborative timing recovery is realized in a 0.13μm 1P8M CMOS logic process. A global timing-recovery block that combines timing-error information from several parallel data channels more than doubles the jitter tolerance bandwidth while consuming <6.4mW/Gb/s from a 1.1V supply.",
author = "Ankur Agrawal and Hanumolu, {Pavan Kumar} and Wei, {Gu Yeon}",
year = "2008",
doi = "10.1109/ISSCC.2008.4523260",
language = "English (US)",
isbn = "9781424420100",
series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",
pages = "468--469+628+451",
booktitle = "2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC",
note = "2008 IEEE International Solid State Circuits Conference, ISSCC ; Conference date: 03-02-2008 Through 07-02-2008",
}