An 8 Gb/s-64 Mb/s, 2.3-4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS

Mrunmay Talegaonkar, Amr Elshazly, Karthikeyan Reddy, Praveen Prabha, Tejasvi Anand, Pavan Kumar Hanumolu

Research output: Contribution to journalArticlepeer-review

Abstract

A burst-mode transmitter achieves 6ns turn-on time by utilizing a fast frequency settling ring oscillator in digital multiplying delay-locked loop and a rapid on-off biasing scheme for current mode output driver. The resistor tuning-based ring oscillator avoids the use of bias voltages and thereby eliminates the related settling time overhead. The calibrated rapid on-off biasing circuit utilizes a fast charging technique to achieve bias voltage settling time of 4ns, resulting in 30X improvement over a diode-connected bias circuit. Fabricated in 90 nm CMOS process, the prototype achieves 2.29 mW/Gb/s energy efficiency at peak data rate of 8 Gb/s. A 125X (8 Gb/s to 64 Mb/s) change in effective data rate results in 67X (18.29 mW to 0.27 mW) change in transmitter power consumption corresponding to only 2X (2.29 mW/Gb/s to 4.24 mW/Gb/s) degradation in energy efficiency for 32 byte long data bursts. We also present an analytical bit error rate (BER) computation technique for rapid on-off links, which uses MDLL settling measurement data in conjunction with always-on transmitter measurements. This technique indicates that the BER bathtub width for 10-12 BER is 0.65 UI and 0.72 UI during rapid on-off operation and always-on operation, respectively.

Original languageEnglish (US)
Article number6893043
Pages (from-to)2228-2242
Number of pages15
JournalIEEE Journal of Solid-State Circuits
Volume49
Issue number10
DOIs
StatePublished - Oct 1 2014

Keywords

  • Bit error rate
  • current mode logic (CML) output driver
  • digital multiplying delay-locked loop (MDLL)
  • digitally-controlled ring oscillator (DCO)
  • energy-proportional operation
  • fast turn-on clock multiplier
  • rapid on-off bias

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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