An 8× 5 Gb/s parallel receiver with collaborative timing recovery

Ankur Agrawal, Andrew Liu, Pavan Kumar Hanumolu, Gu Yeon Wei

Research output: Contribution to journalArticlepeer-review

Abstract

This paper presents the design of an 8 channel, 5 Gb/s per channel parallel receiver with collaborative timing recovery and no forwarded clock. The receiver architecture exploits synchrony in the transmitted data streams in a parallel interface and combines error information from multiple phase detectors in the receiver to produce one global synthesized clock. This collaborative timing recovery scheme enables wideband jitter tracking without increasing the dithering jitter in the synthesized clock. Circuit design techniques employed to implement this receiver architecture are discussed. Experimental results from a 130 nm CMOS test chip demonstrate the enhanced tracking bandwidth and lower dithering jitter of the recovered clock.

Original languageEnglish (US)
Article number5308603
Pages (from-to)3120-3130
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume44
Issue number11
DOIs
StatePublished - Nov 1 2009
Externally publishedYes

Keywords

  • Clock and data recovery
  • High-speed serial link
  • Jitter tolerance
  • Jitter tracking bandwidth
  • Parallel receiver
  • Source-synchronous link

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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