Algorithms transformation techniques for low-power wireless VLSI systems design

Research output: Contribution to journalReview article

Abstract

This paper presents an overview of algorithm transformation techniques and discusses their role in the development of hardware-efficient and low-power VLSI algorithms and architectures for communication systems. Algorithm transformation techniques such as retiming, look-ahead and relaxed pipelining, parallel processing, folding, unfolding, and strength reduction are described. These techniques are applied statically (i.e., during the system design phase) and hence are referred to as static algorithm transformations (SATs). SAT techniques alter the structural and functional properties of a given algorithm so as to be able to jointly optimize performance measures in the algorithmic (signal-to-noise ratio [SNR] and bit error rate [BER]) and VLSI (power dissipation, area and throughput) domains. Next, a new class of algorithm transformations referred to as dynamic algorithm transformations (DAT) is presented. These transformations exploit the nonstationarity in the input signal environment to determine and assign minimum computational requirements for an algorithm in real time. Both SAT and DAT techniques are poised to play a critical role in the development of low-power wireless VLSI systems given the trend toward increasing digital signal processing in these systems.

Original languageEnglish (US)
Pages (from-to)147-171
Number of pages25
JournalInternational Journal of Wireless Information Networks
Volume5
Issue number2
DOIs
StatePublished - Apr 1 1998

Fingerprint

Systems analysis
Digital signal processing
Bit error rate
Energy dissipation
Signal to noise ratio
Communication systems
Throughput
Hardware
Processing

Keywords

  • Architectures
  • Low power
  • VLSI
  • Wireless

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

Algorithms transformation techniques for low-power wireless VLSI systems design. / Shanbhag, Naresh R.

In: International Journal of Wireless Information Networks, Vol. 5, No. 2, 01.04.1998, p. 147-171.

Research output: Contribution to journalReview article

@article{0296aefd7acc4a44a211c19fa6b8e439,
title = "Algorithms transformation techniques for low-power wireless VLSI systems design",
abstract = "This paper presents an overview of algorithm transformation techniques and discusses their role in the development of hardware-efficient and low-power VLSI algorithms and architectures for communication systems. Algorithm transformation techniques such as retiming, look-ahead and relaxed pipelining, parallel processing, folding, unfolding, and strength reduction are described. These techniques are applied statically (i.e., during the system design phase) and hence are referred to as static algorithm transformations (SATs). SAT techniques alter the structural and functional properties of a given algorithm so as to be able to jointly optimize performance measures in the algorithmic (signal-to-noise ratio [SNR] and bit error rate [BER]) and VLSI (power dissipation, area and throughput) domains. Next, a new class of algorithm transformations referred to as dynamic algorithm transformations (DAT) is presented. These transformations exploit the nonstationarity in the input signal environment to determine and assign minimum computational requirements for an algorithm in real time. Both SAT and DAT techniques are poised to play a critical role in the development of low-power wireless VLSI systems given the trend toward increasing digital signal processing in these systems.",
keywords = "Architectures, Low power, VLSI, Wireless",
author = "Shanbhag, {Naresh R}",
year = "1998",
month = "4",
day = "1",
doi = "10.1023/A:1018869519651",
language = "English (US)",
volume = "5",
pages = "147--171",
journal = "International Journal of Wireless Information Networks",
issn = "1068-9605",
publisher = "Springer New York",
number = "2",

}

TY - JOUR

T1 - Algorithms transformation techniques for low-power wireless VLSI systems design

AU - Shanbhag, Naresh R

PY - 1998/4/1

Y1 - 1998/4/1

N2 - This paper presents an overview of algorithm transformation techniques and discusses their role in the development of hardware-efficient and low-power VLSI algorithms and architectures for communication systems. Algorithm transformation techniques such as retiming, look-ahead and relaxed pipelining, parallel processing, folding, unfolding, and strength reduction are described. These techniques are applied statically (i.e., during the system design phase) and hence are referred to as static algorithm transformations (SATs). SAT techniques alter the structural and functional properties of a given algorithm so as to be able to jointly optimize performance measures in the algorithmic (signal-to-noise ratio [SNR] and bit error rate [BER]) and VLSI (power dissipation, area and throughput) domains. Next, a new class of algorithm transformations referred to as dynamic algorithm transformations (DAT) is presented. These transformations exploit the nonstationarity in the input signal environment to determine and assign minimum computational requirements for an algorithm in real time. Both SAT and DAT techniques are poised to play a critical role in the development of low-power wireless VLSI systems given the trend toward increasing digital signal processing in these systems.

AB - This paper presents an overview of algorithm transformation techniques and discusses their role in the development of hardware-efficient and low-power VLSI algorithms and architectures for communication systems. Algorithm transformation techniques such as retiming, look-ahead and relaxed pipelining, parallel processing, folding, unfolding, and strength reduction are described. These techniques are applied statically (i.e., during the system design phase) and hence are referred to as static algorithm transformations (SATs). SAT techniques alter the structural and functional properties of a given algorithm so as to be able to jointly optimize performance measures in the algorithmic (signal-to-noise ratio [SNR] and bit error rate [BER]) and VLSI (power dissipation, area and throughput) domains. Next, a new class of algorithm transformations referred to as dynamic algorithm transformations (DAT) is presented. These transformations exploit the nonstationarity in the input signal environment to determine and assign minimum computational requirements for an algorithm in real time. Both SAT and DAT techniques are poised to play a critical role in the development of low-power wireless VLSI systems given the trend toward increasing digital signal processing in these systems.

KW - Architectures

KW - Low power

KW - VLSI

KW - Wireless

UR - http://www.scopus.com/inward/record.url?scp=0032043239&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032043239&partnerID=8YFLogxK

U2 - 10.1023/A:1018869519651

DO - 10.1023/A:1018869519651

M3 - Review article

AN - SCOPUS:0032043239

VL - 5

SP - 147

EP - 171

JO - International Journal of Wireless Information Networks

JF - International Journal of Wireless Information Networks

SN - 1068-9605

IS - 2

ER -