TY - JOUR
T1 - Algorithms transformation techniques for low-power wireless VLSI systems design
AU - Shanbhag, Naresh R.
N1 - Funding Information:
The author would like to acknowledge the efforts of Manish Goel and Raj Hegde in manuscript preparation. Financial support for this work was provided by the National Science Foundation CAREER award MIP-9623737.
PY - 1998/4/1
Y1 - 1998/4/1
N2 - This paper presents an overview of algorithm transformation techniques and discusses their role in the development of hardware-efficient and low-power VLSI algorithms and architectures for communication systems. Algorithm transformation techniques such as retiming, look-ahead and relaxed pipelining, parallel processing, folding, unfolding, and strength reduction are described. These techniques are applied statically (i.e., during the system design phase) and hence are referred to as static algorithm transformations (SATs). SAT techniques alter the structural and functional properties of a given algorithm so as to be able to jointly optimize performance measures in the algorithmic (signal-to-noise ratio [SNR] and bit error rate [BER]) and VLSI (power dissipation, area and throughput) domains. Next, a new class of algorithm transformations referred to as dynamic algorithm transformations (DAT) is presented. These transformations exploit the nonstationarity in the input signal environment to determine and assign minimum computational requirements for an algorithm in real time. Both SAT and DAT techniques are poised to play a critical role in the development of low-power wireless VLSI systems given the trend toward increasing digital signal processing in these systems.
AB - This paper presents an overview of algorithm transformation techniques and discusses their role in the development of hardware-efficient and low-power VLSI algorithms and architectures for communication systems. Algorithm transformation techniques such as retiming, look-ahead and relaxed pipelining, parallel processing, folding, unfolding, and strength reduction are described. These techniques are applied statically (i.e., during the system design phase) and hence are referred to as static algorithm transformations (SATs). SAT techniques alter the structural and functional properties of a given algorithm so as to be able to jointly optimize performance measures in the algorithmic (signal-to-noise ratio [SNR] and bit error rate [BER]) and VLSI (power dissipation, area and throughput) domains. Next, a new class of algorithm transformations referred to as dynamic algorithm transformations (DAT) is presented. These transformations exploit the nonstationarity in the input signal environment to determine and assign minimum computational requirements for an algorithm in real time. Both SAT and DAT techniques are poised to play a critical role in the development of low-power wireless VLSI systems given the trend toward increasing digital signal processing in these systems.
KW - Architectures
KW - Low power
KW - VLSI
KW - Wireless
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U2 - 10.1023/A:1018869519651
DO - 10.1023/A:1018869519651
M3 - Review article
AN - SCOPUS:0032043239
SN - 1068-9605
VL - 5
SP - 147
EP - 171
JO - International Journal of Wireless Information Networks
JF - International Journal of Wireless Information Networks
IS - 2
ER -