Algorithms transformation techniques for low-power wireless VLSI systems design

This paper presents an overview of algorithm transformation techniques and discusses their role in the development of hardware-efficient and low-power VLSI algorithms and architectures for communication systems. Algorithm transformation techniques such as retiming, look-ahead and relaxed pipelining, parallel processing, folding, unfolding, and strength reduction are described. These techniques are applied statically (i.e., during the system design phase) and hence are referred to as static algorithm transformations (SATs). SAT techniques alter the structural and functional properties of a given algorithm so as to be able to jointly optimize performance measures in the algorithmic (signal-to-noise ratio [SNR] and bit error rate [BER]) and VLSI (power dissipation, area and throughput) domains. Next, a new class of algorithm transformations referred to as dynamic algorithm transformations (DAT) is presented. These transformations exploit the nonstationarity in the input signal environment to determine and assign minimum computational requirements for an algorithm in real time. Both SAT and DAT techniques are poised to play a critical role in the development of low-power wireless VLSI systems given the trend toward increasing digital signal processing in these systems.