Algorithmic noise-tolerance for low-power signal processing in the deep submicron era

In deep submicron (DSM) VLSI technology, deviations in node voltages due to DSM noise can lead to erroneous system outputs in VLSI implementations of DSP and communication algorithms degrading their performance in terms of signal-to-noise ratio (SNR) or bit-error-rate (BER). We present algorithmic noise-tolerance schemes for digital filtering to detect such errors in system output and mitigate their effect on the system performance. The errors in the system output are detected by employing a low-complexity prediction scheme. It is shown that, the proposed scheme improves the performance of the filtering algorithm by up to 10dB with less than 10% hardware overhead. It is also shown that the proposed scheme can be employed to achieve substantial energy savings with marginal degradation in performance by deliberately introducing errors in DSP hardware by overscaling the supply voltage.