Abstract
The world has seen the great success of deep neural networks (DNNs) in a massive number of artificial intelligence (AI) applications. However, developing high-quality AI services to satisfy diverse real-life edge scenarios still encounters many difficulties. As DNNs become more compute-and memory-intensive, it is challenging for edge devices to accommodate them with limited computation/memory resources, tight power budgets, and small form-factors. Challenges also come from the demanding requirements of edge AI, requesting real-time responses, high-throughput performance, and reliable inference accuracy. To address these challenges, we propose a series of efficient design methods to perform algorithm/accelerator co-design and co-search for optimized edge AI solutions. We demonstrate our proposed methods on popular edge AI applications (object detection and image classification) and achieve significant improvements than prior designs.
Original language | English (US) |
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Pages (from-to) | 3064-3070 |
Number of pages | 7 |
Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
Volume | 69 |
Issue number | 7 |
DOIs | |
State | Published - Jul 1 2022 |
Keywords
- AI accelerators
- Deep neural network
- Edge computing
- HW/SW co-design
ASJC Scopus subject areas
- Electrical and Electronic Engineering