Adaptively mapping code in an intelligent memory architecture

Yan Solihin, Jaejin Lee, Josep Torrellas

Research output: Chapter in Book/Report/Conference proceedingConference contribution


This paper presents an algorithm to automatically map code to a generic Processor-In-Memory (PIM) system that consists of a host processor and a much simpler memory processor. To achieve high performance with this type of architecture, code needs to be partitioned and scheduled such that each section is assigned to the processor on which it runs most efficiently. In addition, processors should overlap their execution as much as possible. Our algorithm is embedded in a compiler and run-time system and maps applications fully automatically using both static and dynamic information. Using a set of applications and a simulated architecture, we show average speedups of 1.7 over a single host with plain memory. The speedups are very close and often higher than ideal speedups on a more expensive multiprocessor system composed of two identical host processors. Our work shows that heterogeneity can be cost-effectively exploited, and represents one step toward effectively mapping code to more advanced PIM systems.

Original languageEnglish (US)
Title of host publicationIntelligent Memory Systems - 2nd International Workshop, IMS 2000, Revised Papers
EditorsFrederic T. Chong, Mark Oskin, Christoforos Kozyrakis
Number of pages14
ISBN (Print)3540424067, 9783540423287
StatePublished - 2001
Event2nd International Workshop on Intelligent Memory Systems, IMS 2000 - Cambridge, United States
Duration: Nov 12 2000Nov 12 2000

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


Other2nd International Workshop on Intelligent Memory Systems, IMS 2000
Country/TerritoryUnited States

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)


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