Adaptive cache bypass and insertion for many-core accelerators

Keyphrases

• Many-core Accelerator 100%
• Cache Bypassing 100%
• Adaptive Cache 100%
• System Performance 66%
• GPU Architecture 66%
• Management Policy 66%
• GPU 66%
• Data Sharing 33%
• System Energy 33%
• Performance Efficiency 33%
• Energy Efficiency 33%
• Cache Hierarchy 33%
• Memory Access 33%
• Execution Model 33%
• Caching 33%
• Cache Performance 33%
• Cache Management 33%
• Tion 33%
• Irregular Memory Access 33%
• Limiting System 33%
• GPU Cache 33%
• Massive multithreading 33%
• Memory Latency 33%
• Terns 33%
• L2 Cache 33%
• Access History 33%
• Tag Array 33%
• L1 Cache 33%
• Cache Sensitive 33%
• Extra Bits 33%
• Locality Information 33%
• Polluting 33%

Computer Science

• Many-Core 100%
• Graphics Processing Unit 100%
• Systems Performance 40%
• Memory Access 40%
• Policy Management 40%
• Data Sharing 20%
• Energy Efficiency 20%
• Cache Hierarchy 20%
• Execution Model 20%
• Multithreading 20%
• Memory Latency 20%
• L2 Cache 20%
• L1 Cache 20%