Achieving high instruction cache performance with an optimizing compiler.

Wen-Mei W Hwu, Pohua P. Chang

Research output: Contribution to journalConference article

Abstract

Increasing the execution power requires a high instruction-issue bandwidth, and decreasing instruction encoding and applying some code improving techniques cause code expansion. Therefore, the instruction memory hierarchy performance has become an important factor in system performance. An instruction-placement algorithm has been implemented in the IMPACT-1 (Illinois Microarchitecture Project using Advanced Compiler Technology - Stage I) C compiler to maximize the sequential and spatial localities and to minimize mapping conflicts. This approach achieves low cache miss ratios and low memory traffic ratios for small, fast instruction caches with little hardware overhead. For ten realistic Unix programs, the authors report low miss ratios (average 0.5%) and low memory traffic ratios (average 8%) for a 2048-byte, direct-mapped instruction cache using 64-byte blocks. This result compares favorably with the fully associative cache results reported by other researchers. The authors also present the effect of cache size, block size, block sectoring, and partial loading on the cache performance. The code performance with instruction placement optimization is shown to be stable across architectures with different instruction-encoding density.

Original languageEnglish (US)
Pages (from-to)242-251
Number of pages10
JournalConference Proceedings - Annual Symposium on Computer Architecture
Issue number16
StatePublished - May 1 1989
Event16th Annual International Symposium on Computer Architecture - Jerusalem, Israel
Duration: May 28 1989Jun 1 1989

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Achieving high instruction cache performance with an optimizing compiler. / Hwu, Wen-Mei W; Chang, Pohua P.

In: Conference Proceedings - Annual Symposium on Computer Architecture, No. 16, 01.05.1989, p. 242-251.

Research output: Contribution to journalConference article

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